Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: SP and R
Edited by the Electronicstalk Editorial Team on 21 May 2002
Enhancements speed integrated design solution
Cadence has upgraded its SP and R integrated RTL-to-GDSII design solution to enable designers to produce higher-performance chips in shorter design cycles than ever before
Cadence has upgraded its SP and R (synthesis/place-and-route) integrated RTL-to-GDSII design solution to enable designers to produce higher-performance chips in shorter design cycles than ever before. The new Cadence SP and R technology delivers significantly more powerful timing and signal integrity optimisation, more than twice the performance in synthesis and routing, and next-generation power planning for large, complex ICs.
Related stories
Design platform enable DDR integration at 65nm
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform
Methodology combines design with verification
Fujitsu Kyushu Network Technologies is using the Cadence Incisive plan-to-closure methodology for SystemVerilog verification in RTL logic design teams
This release of Cadence SP and R technology includes enhancements to BuildGates synthesis, Physically Knowledgeable Synthesis (PKS), Silicon Ensemble and SoC Encounter place-and-route systems which shorten the time it takes to design multi-million-gate digital ICs.
Cadence SP and R has enhanced performance and features to address the design challenges of sub-0.13-micron process technology.
Physical synthesis and routing performance improvements include an average of two times the speed in physical synthesis and advanced high-level optimisations for superior quality of results.
A new multiple-CPU capability speeds up core Silicon Ensemble routing performance as much as 10 times, and complements the multi-CPU capability in NanoRoute.
A flexible and productive next-generation power planner provides innovative features enabling maximised flexibility and productivity in power planning and power routing.
Further reading
Software takes holistic view of PCB design
System interconnect design platform adds new capabilities at all stages of printed-circuit board design
Single simulator covers all IC technologies
End-to-end simulation and verification software for custom IC uses a common database of netlists and models to simulate analogue, RF, memory and mixed-signal designs
Kit cuts the cost of low-power IC design
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort
Post-route signal integrity optimisation tightly integrates signal integrity prevention, advanced crosstalk analysis - such as noise-on-delay and glitch analysis - with CeltIC technology and timing-driven post-route repair for better quality of results.
The embedded common engines used during all phases of signal integrity analysis, prevention, and correction help ensure rapid signal integrity closure and reduces multiple iterations for faster time-to-market.
Physically knowledgeable power analysis and optimisation concurrently optimises designs for timing and power consumption using physical information.
The integration of power optimisation in physical synthesis delivers early predictability for power consumption and 20 to 60% power reduction.
This is critical for chip designers targeting power-sensitive applications, such as handheld consumer products and satellite systems.
The physically knowledgeable, low-power synthesis supports comprehensive RTL optimisations, such as clock-gating, its integration with clock-tree synthesis, and sleep mode, as well as gate-level optimisations.
Concurrent optimisation ensures that the power reduction is achieved without affecting the timing performance.
Advanced datapath optimisation integrated in logic and physical synthesis enables concurrent optimisation of advanced datapath and control logic in a single synthesis solution.
This allows engineers to describe complex datapath design along with surrounding control logic using simple extensions to Verilog 2001 and VHDL.
The result is high performance datapath and control logic without the problems of multiple flows and manual intervention.
In addition, the datapath and control are optimised in the same timing context, eliminating multiple iterations.
BuildGates Extreme synthesis delivers high performance synthesis, multi-million-gate capacity, more than two times faster turnaround time, and integrated low-power and advanced datapath optimisation to satisfy advanced design performance needs.
Routing enhancements satisfy requirements for sub-0.13-micron process technology, providing designers with a multitude of automated features to handle requirements now mandated by foundries for leading-edge designs.
These include complex wide-wire spacing rules, minimum area rules, double-cut via requirements for signal wires and pins, advanced hierarchical process antenna rules, new requirements for copper process technologies, metal density checking and fill, and metal slotting/splitting.
"With this new release of our SP and R technology, Cadence is advancing the bar for IC design and implementation at 0.13-micron and below technology", said Eric Filseth, vice president of SP and R marketing at Cadence.
"The integrated signal integrity prevention, analysis and repair, and performance enhancements in synthesis and routing deliver a superior design flow to our customers".
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Related Business News
Icoa Is Partnering With Anchorfree To...
...Enhance And Monetize Thousands Of Wi-fi Hotspots. Icoa, Inc., a national provider of wireless broadband Internet access and managed network services in high-traffic public locations, and AnchorFree Inc., a rapidly growing Wi-Fi community powered by advertising, have announced today that they are partne
Eds Sales Take A Tumble
Dave Friedlos, Computing , Thursday 17 May 2007 at 00:00:00 But experts say downturn may reflect market weakness, writes Dave Friedlos Outsourcing giant EDS has released disappointing first-quarter figures showing slower growth and fewer con
Sweet specialist sees growth spurt
Lara Williams, Computing , Thursday 17 May 2007 at 00:00:00 Confectionary company IT infrastructure overhaul accommodates rapid growth Confectionery supplier Bon Bon Buddies has overhauled its IT infrastructure to cope with rapid growth whic
Canon takes a better picture of its supply chain
Lara Williams , Computing , Thursday 17 May 2007 at 00:00:00 Imaging specialist improves sales forcasting by 20 per cent Imaging specialist Canon has improved the accuracy of product sales forecasting by more than 20 per cent using supply ch
Search the Pro-Talk network of sites
