Family group to unify verification

The Univers product family is a unified verification solution for both hardware and embedded software design of SoCs.

The Univers product family is a unified verification solution for both hardware and embedded software design of systems-on-chip (SoCs).

Adveda's flagship product is its Miss Univers, a "marvellous integrated system simulator", which is a unified hardware/software coverification tool.

Miss Univers performs combined hardware and software cycle-accurate simulations at 100 times the simulation speed of other coverification solutions, while also providing unique debugging features.

It will be demonstrated at DATE 2004.

Hardware software codesign is a burgeoning area of leading edge SoC design.

Current methods for hardware software coverification involve connecting the instruction set simulator and debugger with the hardware simulator by means of yet a third tool, resulting in three different simulation kernels.

Miss Univers is the first unified hardware software coverification solution with only one simulation kernel, directly steering RTL models and ISSs.

This breakthrough technology eliminates the unwieldy integration overhead that engineers have historically faced both in terms of awkward data exchange and a loss of speed from the communication overhead.

"The Univers family was designed to meet the challenges of the most complex SoC designs", said Cor Schepens, Adveda's CEO.

"With Miss Univers' integrated RTL simulator, SoC designers can run simulations in hours which would otherwise take weeks with traditional RTL simulators.

This speed increase can break the coverification bottleneck of hardware software codesign by shaving months off of an entire development cycle.

It will also allow greater time for more thorough testbenches which are critical to ensure first silicon success".

Adveda's Miss Univers hardware software coverification solution combines fast hardware simulation and fast instruction set simulators using a unique architecture, which employs only one simulation kernel in a unified development environment.

This next-generation approach results in unsurpassed coverification speeds and unique debug features.

Adveda's hardware simulator is a cycle-based RTL simulator, built according to the latest technologies, which can accelerate an RTL simulation up to 100 times the speed of traditional event-driven simulators.

The RTL simulator can handle the full synthesisable RTL syntax, including multiple asynchronous clocks, asynchronous resets as well as tristate signals.

The first production release will support the VHDL RTL language.

The Instruction Set Simulators are built with Adveda's proprietary technology and provide very fast cycle-accurate ISS of over one million cycles per second combined with robust debugging capabilities.

The integrated development environment (IDE) contains editors for both the embedded software and the RTL source code, and all windows have 'colour coding' for ease of reading.

The IDE contains all debug functionality that is common to state-of-the-art tools and has several extensions that go beyond this.

As the software and hardware simulation is truly unified in one simulation kernel, the debug functionality of both worlds can be mixed.

For instance, it is possible to view registers from an ISS in the waveform view mixed with hardware signals.

In turn, it is possible to select registers in the hardware and display it within the register view of the processor.

"We and some of our key customers have beta-tested the Adveda software debugging tools together with an Adveda-generated ISS for our Saturn DSP", remarked Rob Woudsma, CTO of Adelante Technologies.

"We were astonished by the simulation speed of the ISS and the unique debugging features of Adveda's IDE, which will accelerate the development of the software applications of our customers.

We are currently also investigating Adveda's fast VHDL simulation and coverification technology".

The Univers family is currently available to limited customers, and full production release will be in March 2004.

Pricing for Miss Univers time-based licences (TBLs) starts at $25,000 per year.

The stand-alone "marvellous RTL simulator", Mrs Univers VHDL, TBLs start at $10,000 per year.

The "marvellous advanced debugger and model" environment, Madam Univers, starts at $1250.

The instruction set simulators are sold separately.

The Univers family is supported on the Sun Solaris, HP-UX, Microsoft Windows NT/2000/XP platforms.

Back to top