Start with the news release SoC platform speeds designs to market from Toshiba Electronics Europe, which we summarised at the time by saying "The CPS platform allows designers to take an overall system view of an SoC and perform a number of traditionally sequential and isolated tasks in parallel.". Several months prior to that, we featured the news release Shrink to 40nm increases FPGA capabilities from Altera Europe: "The Stratix IV family has up to 680K logic elements, 2x bigger than Altera's Stratix III family, which currently comprise currently the largest FPGAs on the market.".
 
In January 2008, we covered the news from Emulation and Verification Engineering (EVE) - take a look at Coverification and virtual platforms come together which says: "Companies will to work together to introduce complementary transactor strategies and roadmaps based on the emerging OSCI TLM2 standard for model interoperability.".
 
Take a look also at the news release from Cadence Design Systems, Emulator accelerates IC verification, as well as EVE CEO hails 2006 as stunning year from Emulation and Verification Engineering (EVE), and ST leads European embedded project from STMicroelectronics.