Forte to demonstrate synthesis software at event

Forte Design Systems is to demonstrate its SystemC high-level synthesis software for hardware and electronic system level (ESL) design at the Electronic Design and Solution Fair on 28-29 January 2010.

The company will also showcase its register transfer level (RTL) datapath synthesis software and arithmetic intellectual property at the event, which will be held at the Pacifico Yokohama in Kanagawa, Japan.

Continuous demonstrations of Cynthesizer, high-level synthesis silicon will highlight its features, including support for complex control and datapath designs with accurate modelling capabilities with SystemC.

Forte will also debut the first release of Cellmath Designer datapath synthesis under the Forte brand.

Cellmath Designer uses advanced algorithms and patented arithmetic IP, including fixed and floating point functional units, to improve the quality of results on existing RTL designs by reducing area and power usage.

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