Product category: Design and Development Software
News Release from: Atrenta | Subject: SpyGlass
Edited by the Electronicstalk Editorial Team on 03 November 2006
Software spots critical SoC issues early
Cray has adopted the SpyGlass platform for its next generation ASIC projects.
Cray has adopted the SpyGlass platform for its next generation ASIC projects Using SpyGlass platform, including SpyGlass-Constraints and SpyGlass-DFT, Cray's design teams managed to address critical issues early at RTL on a 30-million-gate design, thus preventing a domino effect of delays and iterations later in implementation and verification phases
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
Related stories
Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
"For our large SoCs, we needed a methodology to manage the increased complexity of the designs".
"SpyGlass, combined with Constraints and DFT tools, is helping us jumpstart design closure at the RTL phase", said Peg Williams, Cray Senior Vice President of Research and Development.
"We selected Atrenta because its comprehensive tool suite was expected to help us resolve problems earlier in the design cycle, preventing costly downstream implementation issues".
Further reading
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.
"SpyGlass-Constraints enabled us to detect and correct critical issues with our design constraints including verification of false and multi-cycle paths".
"SpyGlass-DFT provided test coverage at the RTL-level and helped address scan and testability issues early in the design cycle".
"Overall, the SpyGlass tool suite provided us with state-of-the-art design analysis".
"We plan to continue its use into our next-generation SoCs".
"We are excited to have the market leader for supercomputers adopt Atrenta's solution", stated Dr Ajoy Bose, Atrenta's Chairman, President and CEO.
"It reinforces our commitment to providing the best early design closure solution for critical design challenges".
"Partnering with such industry leaders as Cray gives Atrenta a keen insight into the emerging design issues to help shape our roadmap for our next-generation solutions".
SpyGlass is the industry standard for early design analysis with most in-depth analysis early at RTL design phase.
SpyGlass greatly reduces the late stage risks in developing complex multi-million-gate, nanometre-scale ICs, enabling companies to build better products, faster and more economically.
SpyGlass accurately detects design issues at the point of creation, which is at RTL.
SpyGlass-Constraints helps early design closure by ensuring high quality implementation through constraint analysis and management, reduced manual effort with first pass constraint creation, and reduced silicon timing risk through false path validation.
SpyGlass-DFT is the first solution enabling IC designers to build testability into their designs up-front, at the register transfer level (RTL).
Created specifically for logic designers, it lets users apply robust design-for-test methods and ensures high-test coverage without becoming test experts themselves.
SpyGlass-DFT not only detects testability issues - it can also automatically correct them.
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