Product category: Design and Development Software
News Release from: Atrenta | Subject: SpyGlass DFT
Edited by the Electronicstalk Editorial Team on 17 January 2002
Analysis tool checks testability of RTL
code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
SpyGlass DFT is the latest addition to Atrenta's popular SpyGlass predictive analysis tool that adds two new engines to find testability issues at RTL (register-transfer level) that normally only can be identified at the gate level According to Atrenta, no other tool can provide the comprehensive range of testability analysis offered by SpyGlass DFT
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
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Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
SpyGlass DFT includes rules for ATPG and BIST.
If RTL designers don't properly apply testability rules at the initial design stage, the design can have poor test coverage or even be untestable until extensive changes are made.
By letting designers write their RTL code to comply with testability rules before lengthy synthesis and simulation cycles, SpyGlass DFT can cut weeks or months off design cycles, eliminating or reducing gate-level debug and costly schedule delays.
Further reading
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.