Product category: Design and Development Software
News Release from: Atrenta | Subject: SpyGlass SoC
Edited by the Electronicstalk Editorial Team on 22 May 2002
Tool brings order to mixed-IP SoC
designs
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design.
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design By using SpyGlass SoC to create a logical virtual prototype, designers can predict and eliminate problems that normally only show up much later in the design process
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
Related stories
Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
With SpyGlass SoC, design teams can cut their overall SoC design times by 20 to 30%, according to company estimates.
"Integrating multiple blocks into a single SoC design has become a huge productivity issue", stated Darren Wedgwood, EDA Development and Synthesis Methodology Manager, Motorola Semiconductor.
"With SpyGlass SoC, we can identify synthesis, DFT and Motorola Semiconductor Re-Use Standards compliance issues up front, when each block is created.