Product category: Microprocessors, Microcontrollers and DSPs
News Release from: Atmel Corporation | Subject: AT91SAM9263
Edited by the Electronicstalk Editorial Team on 14 December 2006
Increase internal data bandwidth
Atmel has announced the newest member of its SAM9 family, the AT91SAM9263 embedding a 200 MIPS ARM926EJ-STM-based microcontroller
Atmel has announced the newest member of its SAM9 family, the AT91SAM9263 embedding a 200 MIPS ARM926EJ-STM-based microcontroller that overcomes the bottlenecks that occur with conventional ARM9TM-based MCUs in graphically-interfaced, data-intensive applications such as networked medical monitoring equipment and GPS navigation systems The AT91SAM9263 employs 27 DMA channels including Atmel's 18-channel peripheral DMA controller (PDC), a 9-layer bus matrix, and two additional busses for data- and instruction-tightly-coupled-memories (TCMs) to boost CPU performance and provide on-chip data transfer rates of up to 41.6 Gbps
This article was originally published on Electronicstalk on 18 Nov 2005 at 8.00am (UK)
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Networking peripherals include a 12 Mbps USB host and device, a 10/100 Ethernet MAC and a 1 Mbps control area network (CAN).
There are also four USARTs, two 50 Mbps serial parallel interfaces (SPI), CompactFlash, SDIO (MCI) and a two-wire interface (TWI) which can be connected to external wired and wireless communication modules like GPRS modem and Wi-Fi.
Peripheral DMA Controller Relieves CPU of Peripheral-to-Memory Transfers - Conventional ARM9-based processors use load/store instructions that require at least 80 CPU cycles to transfer a single byte of data between memory and a peripheral.
Running at 200 MHz with a bus frequency of 100 MHz, these processors typically reach the limit of their capability at about 20 Mbps even with the memory management unit and instruction- and data-cache controllers enabled.
Atmel's AT91SAM9263 integrates 18 simple, silicon-efficient, single-cycle, peripheral DMA controllers (PDC), five DMA controllers with burst mode support to the USB host, Ethernet MAC, camera interface, LCD controller and 2D graphics controller, plus a memory-to-memory DMA controller with burst mode, scatter-gather and linked lists support.
The DMA controllers completely off-load the execution of data transfers between external serial interfaces and memories.
At a 20 Mbps data rate, Atmel's SAM9263 still has 88% of its MIPS available for application execution.
Atmel has implemented 11 busses and 96 Kbytes of on-chip scratchpad SRAM on the AT92SAM9263.
The SRAM can be partly configured as tightly-coupled data and instruction memory (TCM).
The busses provide multiple parallel on-chip data transfer channels and a total on-chip bandwidth of 41.6 Gbps.
The AT91SAM9263 has two external bus interfaces (EBI): one for the system memory and one for the human interface.
The second EBI eliminates the need for the LCD controller and CPU to share memory and can increase available CPU MIPS by 20% to 40%.
The AT91SAM9263 is available now in a 324-ball BGA package and is priced at sub USD10 for 100K parts.
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