Product category: Design Services
News Release from: Asset InterTech | Subject: European design-for-test lab
Edited by the Electronicstalk Editorial Team on 14 February 2007

Lab assesses designs for testability

Design-for-test lab reduces the time to market for new products by identifying JTAG testability issues before prototypes are assembled

Asset InterTech has opened its first European design-for-test (DFT) lab just outside London. By validating the JTAG infrastructure in chip and printed circuit board designs, Asset's DFT lab reduces the time to market for new products by identifying JTAG testability issues before prototypes are assembled.

Building on the success of its recently opened DFT lab in the USA, the European lab offers a free analysis along with design recommendations on preprototype designs.

This analysis ensures that the JTAG infrastructure can be effectively deployed in its traditional structural test applications and in advanced applications that take advantage of the JTAG infrastructure, such as the testing of high-speed AC-coupled serial buses (IEEE1149.6), Intel Interconnect Built In Self Test (IBIST), system-level remote JTAG testing, concurrent programming based on the IEEE1532 standard and others.

'In recent years as chip geometries have shrunk and board designs have gotten denser, boundary-scan test has become a critical tool for manufacturers'.

'In fact, there are a number of advanced test and programming methodologies that take advantage of the JTAG infrastructure'.

'These new test technologies can't perform their functions without a properly designed JTAG infrastructure', said Reg Waller, Asset's European Director.

'By ensuring the soundness of a design's JTAG capabilities, the lab delivers systems to market faster'.

'In the past, testability deficiencies were often not found until first samples or prototypes were built'.

'Then, the deficiencies would have to be addressed and sometimes another round of prototypes built'.

'This is a time-consuming process, but it can now be avoided'.

Asset's European DFT lab is located in Welwyn Garden City, Hertfordshire.

The free testability analysis is available to first-time users of boundary scan.

Kent Zetterberg has been named manager of the lab.

The analysis is performed with Asset's DFT analyser, the industry's only tool that automatically verifies the JTAG testability of board designs.

The accuracy of a chip design's Boundary-Scan Description Language (BSDL) file is verified with the BSDL validation service, a collaborative effort of Asset and Agilent Technologies.

In addition, other tools can be applied to board and chip designs to validate their JTAG capabilities.

'We can offer a free first-time design analysis because DFT analyser, in most cases, reduces the weeks it takes to manually complete a testability analysis and produces a thorough report in a matter of hours', Zetterberg said.

'In addition, the reports we provide are not just simple test coverage reports which are typical of some test tools'.

'Our analysis includes design recommendations that improve test coverage and ensure that the JTAG infrastructure embedded in a design can be utilised by other test and programming methodologies'.

• Asset InterTech: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page

Search the Pro-Talk network of sites

Put your news on Electronicstalk  |   Advertise  |   Get the free Electronicstalk newsletter
Electronicstalk Home  |   About Electronicstalk  |   Copyright © 2000-2007 Pro-Talk Ltd, UK