Product category: Design and Development Software
News Release from: ARC International | Subject: SoC development platform
Edited by the Electronicstalk Editorial Team on 22 October 2002
Development platform aims for
SoCs in half a year
At the heart of ARC's next-generation SoC development platform is the newest version of the ARCtangent-A5 user-customisable 32bit RISC/DSP microprocessor core
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The platform also includes configurable software-development tools, a real-time operating system (RTOS), network-protocol stacks, USB and Ethernet peripherals with device drivers. ARC's next generation SoC platform directly supports the company's mission to provide customers with a single SoC development platform where design cycles of six months or less are critical.
By significantly reducing the number of IP suppliers that customers have to deal with, development costs and overall design risks are significantly reduced.
"While many companies offer a few IP building blocks via third-party relationships, our long-term strategy has always focused beyond our user-customisable RISC/DSP processor to integrate virtually all of the necessary software, peripherals, tools and platforms to deliver an optimised, single-source development environment for the SoC developer", said Mike Gulett, President and Chief Executive of ARC International.
"By obtaining all of the required IP from a single, reliable source, developers save valuable integration time, reducing risk and cost.
When an SoC design is required in six months or less, our integrated development platform is the one to choose".
Each hardware and software building block has been fully tested and integrated into a single-software development tool chain.
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ARC will be demonstrating its next-generation SoC development platform next month at Electronica, showcasing the latest generation of the ARCtangent-A5 processor, the ARChitect processor configuration tool for integrating peripheral IP such as Hi-Speed USB 2.0 and Ethernet, and a new GUI-enhanced version of the popular MetaWare SeeCode debugger.
Aimed at ASIC and SoC products, the ARCtangent-A5 user-customisable 32bit RISC/DSP core delivers high performance with compact code size.
It inherits the feature set of the previous generation ARCtangent-A4 processor, but adds powerful new capabilities, including the ARCompact instruction set, more instruction slots for improved extensibility, peripheral support and additional DSP instructions and features.
The optimised, mixed 16/32bit code density ARCompact instruction set architecture (ISA) reduces code size by more than 30% when compared with a 32bit RISC such as the ARCtangent-A4 processor.
The newest version of the ARCtangent-A5 processor supports the emerging, open-standard BVCI protocol and will be enhanced with optional amba bus support later this year.
By supporting both popular high-level bus standards, developers will be able to easily connect their ARCtangent-based designs to a wider variety of in-house or third-party IP in faster time.
With optional DSP extensions, the ARCtangent-A5 processor provides developers with a highly integrated and unified RISC/DSP system suitable for a wide range of communications and consumer applications.
These include voice over packet (VoP), digital wireless (2.5/3G baseband, 802.11x wireless LAN etc), digital imaging and DVD (JPEG, JPEG2000, MPEG 2, MPEG 4 etc), and digital audio (MP3, AAC, WMA, AC-3 etc).
The MetaWare SeeCode debugger was one of the first with the ability to debug single or multiprocessor systems.
The enhancements made to the graphical user interface (GUI) include consolidated windows within a single frame, convenient tabs for browsing through tiered windows, and offers more control by providing expanded save session settings as well as a wizard setup utility to configure multiprocessor support.
ARC's next-generation SoC development platform is optimised to support today's most popular applications.
Using the easy-to-use, GUI-based ARChitect processor configuration software tool, developers can quickly integrate custom extension instructions, condition codes, auxiliary registers and ARC's pre-integrated, application-specific peripheral soft IP blocks, including USB and Ethernet.
ARC's pre-integrated soft IP blocks remove the time-consuming and costly task of having to integrate and verify IP cores from multiple IP suppliers, and provides developers an efficient platform to focus on differentiating their application-specific logic.
The soft format of the IP also means that the developer has complete visibility of the Verilog/VHDL RTL source code and the choice of almost any fabrication process or vendor.
(This was Electronicstalk's Top Story on 22 October 2002).
(This was Electronicstalk's Top Story on 22 October 2002)
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