Product category: Electronics Manufacturing Services
News Release from: AMI Semiconductor | Subject: FPGA-to-ASIC conversion
Edited by the Electronicstalk Editorial Team on 17 November 2006
Cell-based ASICs drop in for FPGA
replacement
AMI Semiconductor can now convert 1.2V, 90nm FPGAs to 130nm cell-based ASICs.
AMI Semiconductor can now convert 1.2V, 90nm FPGAs to 130nm cell-based ASICs This competency supports OEMs moving from expensive, high-density FPGAs for prototyping to more cost-effective ASICs for production
This article was originally published on Electronicstalk on 23 Jan 2002 at 8.00am (UK)
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Array aimed at FPGA conversions
AMI Semiconductor (AMIS) has launched a 0.18-micron hybrid gate array for medium-density high-speed 1.8V ASICs and FPGA-to-ASIC conversions.
ASIC conversion cost reduces FPGA designs
Anchor Bay Technologies has achieved tape-out success on two of its video processing scaler ASICs using AMI Semiconductor's FPGA-to-ASIC conversion technology.
AMIS is the first company to provide drop-in replacement components for Altera and Xilinx 90nm FPGAs targeting communications (wired and wireless telecomms and datacomms) and military/commercial avionics application-markets.
AMIS ASICs match the core voltage, package and IP of the original FPGAs, reducing customer costs and power consumption as they move from prototype to production silicon.
"Many design engineers select FPGAs for prototyping, but once their product is ready to move into production they find that conversion to cost-effective ASICs can be painful, time consuming and expensive".
Further reading
Clock generators for embedded communications
AMI Semiconductor (AMIS) has expanded its clock generator product line with a broad family of low-cost 1- and 2-phase-lock loop (PLL) clock ICs.
Clock generator saves space in portable designs
AMI Semiconductor (AMIS) has introduced a low-cost clock generator that will save space and reduce component count in high-performance MPEG-2 applications such as DVD players.
"We are the partner that takes the pain out of FPGA-to-ASIC drop-in conversions with our flexible design interface and key IP functions", said Mike O'Neill, Senior Vice President of Structured Digital Products at AMI Semiconductor.
"Our customers are increasingly taking advantage of our hybrid design flow to combine FPGA subsystem prototypes with ASIC IP to create highly integrated ASIC solutions".
AMI Semiconductor's standard cell product technology supports a wide range of I/O standards including SSTL, HSTL, LVPECL, and LVDS.
Memory compilers and register file memories with integrated BIST and redundancy support a wide range of sizes and applications.
High-speed, low-jitter PLLs are integrated with clock-tree synthesis to support high-performance system operation.
Advanced digital clock management functions employing DLL technology will complete the FPGA timing generator conversion capability.
DDR2 PHYs and controllers interface to industry-standard off-chip memories.
PCI-Express serdes running at 2.5Gbit/s will be supported from the physical layer to the transaction layer via the PIPE interface.
A full range of 32bit processors and supporting peripherals are available to round out the product offering.
Moving forward, the IP portfolio will grow to include Gigabit Ethernet, XAUI, USB 2.0, and other high-speed interfaces.
In addition to supporting a traditional RTL design flow, inputs from a variety of sources can be accepted as well, including RTL designs and netlists targeting other ASIC and FPGA technologies.
AMI Semiconductor's hybrid design flow includes full design for test (DFT) capability for at-speed test, memory BIST, timing-driven layout, clock-tree synthesis, and signal-integrity checking.
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