|
Editor's note: Readers of the free Electronicstalk weekly email newsletter will have read this news the week it was announced. Click here to request to be added to the circulation.
The IBM 405LP is a scalable Embedded microprocessor with advanced features to reduce both active and standby power.
The device, available from Acal Semiconductors, is ideally tuned for low power, remote and handheld application needs.
Combining dynamic voltage-frequency scaling, a new on-chip power management controller and software controlled clock gating with integrated hardware accelerators, the 405LP enables power-efficient operation without compromising end product performance.
Based on the IBM 405 32bit RISC CPU core, the 405LP features two 16K instruction and data caches, and uses IBM's CoreConnect bus architecture to interface with on-chip peripherals including a touch screen interface.
The ability to dynamically scale voltage and frequency is crucial to the 405LP's low power operation, making the 405LP suitable for many intelligent appliances including remote and handheld instruments.
At the minimum operating voltage of 1.0V, power consumption is 53mW at up to 152MHz operating frequency.
Maximum voltage is 1.8V, requiring 500mW for 380MHz performance.
The PLL and clocking subsystem is tailored to support voltage and frequency scaling while generating high clock frequencies.
The distribution of on-chip clocks can be controlled by software to deliver multiple clock frequency domains to groups of IP blocks.
Clock gating is implemented at a register level and an IP core level that allows whole IP blocks not in use to be shut down until needed, thus lowering active power considerably.
A new standby power management controller is also implemented.
This provides several modes of operation including freeze, power down hibernation, and a new cryo mode, similar to a flash-freeze state but with "instant-on" capability.
Under software control, this mode can save the register state of the system in external nonvolatile memory, before removing power to the logic core.
The states are restored in less than 200us when required.
Integrated hardware accelerators allow system architects to minimise the operating frequency and system memory requirements when implementing complex algorithms.
Reducing the operating frequency saves power and enhances reliability by reducing heat generation.
The 405LP includes a speech language accelerator for speech recognition, a cryptography accelerator supporting DES and triple-DES encryption algorithms, and the IBM CodePack code compression core that reduces system memory requirements by applying instruction compression.
|
|
