Product category: Design and Development Software
News Release from: AccelChip | Subject: DSP Synthesis 2005.4 with IP-Explorer
Edited by the Electronicstalk Editorial Team on 13 October 2005
Software cuts guesswork from
IP block based design
New technology is claimed to provide unparalleled automation for DSP applications in FPGAs and ASICs
AccelChip, the industry's leading provider of semiconductor intellectual property (IP) and software for Matlab and Simulink DSP algorithms targeting silicon, has announced new technology claimed to provide unparalleled automation for DSP applications in FPGAs and ASICs. Extending the company's leadership in model-based design solutions, AccelChip DSP Synthesis 2005.4 with IP-Explorer technology is available immediately.
This article was originally published on Electronicstalk on 13 October 2005 at 8.00am (UK)
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Implementing DSP algorithms in silicon requires careful selection of IP blocks based on their specifications in the context of the target application.
Prior to IP-Explorer designers were required to have extensive knowledge about the blocks' characteristics across a wide range of system parameters and silicon choices.
Combining IP-Explorer Technology with AccelChip DSP Synthesis software automates and extends upward the design space exploration process to accommodate macro-architectures, or functional variants of mathematical building blocks such as sine, log and divide functions.
With the new technology, AccelChip's DSP Synthesis automatically selects and inserts the optimal AccelWare DSP IP implementation for each function in the design based on system requirements such as frequency, throughput, bit width, area and sample rate.
'AccelChip has always been unique in that we enable customers to code and explore architectures at the macro-level for functions like FFT, filters and trig functions using our AccelWare generators', said Michael Bohm, AccelChip's CTO and Vice President of Product Development.
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'On the other hand, C-based tools only allow tradeoffs to be made at the micro-architecture level or multiplier and adder level'.
'AccelChip's new IP Explorer technology has taken the trial-and-error out of using IP blocks by enabling the tool to select from various macro-architectures depending on specific design and system requirements'.
AccelChip is delivering on the promise of architectural synthesis.
For example, with IP-Explorer Technology, when an algorithm uses a sine function, the tool chooses between Cordic, linear-interpolated lookup table, and bipartite table implementations, and selects the appropriate bit widths based on the floating-point model.
It then even automatically inserts pipeline registers when needed to hit the performance and area goals.
Combining IP optimisation and architectural synthesis is an entirely new level of automation.
The IP-Explorer technology will save customers tremendous time and considerable effort getting complex DSP designs to market.
IP-Explorer uses extensive heuristic modelling based on over 6000 AccelChip and customer designs.
AccelChip's automated IP development system runs all possible combinations of AccelWare against these designs using the latest versions of the most popular design tools to determine silicon results.
The resulting database is used by IP-Explorer to select the optimal macro-architecture as a starting point for the design.
If system requirements change during product development, the design is automatically updated to new architectures if required.
IP- Explorer technology has been added to the AccelWare Building Block Toolkit, supporting trigonometric, logarithmic and division functions.
Heuristic modelling will be added to the AccelWare Signal Processing, Communications and Advanced Math Toolkits in upcoming releases.
'AccelChip's Matlab-based synthesis solution extends Xilinx's Simulink-based tool, System Generator for DSP, by automating the selection of models and their parameters for algorithms written in Matlab', said Omid Tahernia, Vice President and General Manager, Xilinx DSP Division.
'Our mutual customers are using this combination of model-based design solutions to accelerate the design of radar, sonar, GPS and wireless communication systems'.
'By using IP-Explorer technology, designers can now create smaller, faster designs in less time when targeting Xilinx FPGAs'.
Version 2005.4 of AccelChip DSP Synthesis with IP-Explorer and AccelWare IP Generator Toolkits is now shipping.
Current AccelChip customers on support will receive the new release at no additional fee.
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