Design and Development Software

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PAL simplifies FPGA application interfacing

Celoxica has announced its platform abstraction layer (PAL) strategy for FPGA and system independent reconfigurable designs

News from Celoxica (20 June 2001)

Libero sweeps up full set of FPGA design tools

Libero is Actel's next-generation integrated design environment for field-programmable gate array (FPGA) development and design Brochure available

News from Actel Europe (19 June 2001)

Design suite extended to latest FPGAs

Celoxica has extended its DK1 design suite for the rapid design of reconfigurable hardware to support Xilinx Virtex II customers

News from Celoxica (19 June 2001)

SoC system optimised for knowledge management

Mentor Graphics has released version 3.0 of its QuickUse development system (QDS) Brochure available

News from Mentor Graphics UK (19 June 2001)

Monterey gathers its partners in innovation

The Monterey Design Systems Partners in Innovation programme aims to bring together companies involved in IC development and ASIC design that have complementary and innovative technology

News from Monterey Design Systems (19 June 2001)

Synopsis expands design flow solutions

Synopsys has completed its RTL-to-GDSII flow by introducing two high-performance tools built into Physical Compiler: Route Compiler and ClockTree Compiler

News from Synopsys (19 June 2001)

System verifies effective use of IP

Mentor Graphics QuickUse IP qualification system (QuickUse-IQ) is designed to automate the intellectual property (IP) qualification process Brochure available

News from Mentor Graphics UK (18 June 2001)

TOPS: synthesis flow fully automated

Synplicity has highlighted details of a second-generation physical synthesis technology for programmable logic designers, the first such technology in the industry

News from Synplicity (15 June 2001)

Partners to accelerate FPGA-to-ASIC retargeting

AMI Semiconductor and Synplicity plan to jointly develop, test and promote a next-generation design flow to solve new performance and productivity needs related to high-density FPGA conversions

News from Synplicity (14 June 2001)

Half of all European electronic products ship late

Half of all European electronic products ship late and a quarter of European electronic designs hit the market with known bugs, according to a survey funded by EDA vendors

News from Mentor Graphics UK (14 June 2001)

Verplex seeks acceptance for OVL library

Verplex Systems has contributed its Open Verification Language (OVL) library to electronics industry standards organisation Accellera

News from Verplex Systems (13 June 2001)

Mentor first with support for new MIPS processor

Mentor Graphics says it will be first to provide a coverification processor support package (PSP) for the new MIPS32 4KE family of embedded processor cores from MIPS Technologies Brochure available

News from Mentor Graphics UK (13 June 2001)

Monterey is Wizard for Fujitsu's SoCs

Fujitsu has purchased Monterey Design Systems IC Wizard for hierarchical design planning of multi-million-gate integrated circuits

News from Monterey Design Systems (13 June 2001)

Pattern optimisation enhances ATPG tool

FastScan 2001.2 is the latest version of the automatic test pattern generation (ATPG) tool from Mentor Graphics for improving test coverage in ASIC, IC and SoC designs Brochure available

News from Mentor Graphics UK (12 June 2001)

Entry-level schematic-design software

Eplan Compact is the newly released entry-level version of the leading software system for electrical schematic design from Rittal Brochure available

News from Rittal (11 June 2001)

Synthesis solution supports latest FPGAs

Synopsys has upgraded its FPGA synthesis solution: FPGA Compiler II and FPGA Express

News from Synopsys (8 June 2001)

Synplicity adds support for Linux

Synplicity is to add support for the Linux operating system to its entire portfolio of synthesis and prototyping products

News from Synplicity (7 June 2001)

STMicroelectronics standardises on Mentor

STMicroelectronics has standardised on a mixed-signal design methodology based on the Mentor Graphics ADVance MS, ModelSim, Eldo RF and Mach TA tools

News from Mentor Graphics UK (7 June 2001)

Sign-off solution sorts submicron bugs

Avant! Corp claims that Star-Rail is the industry's first ultra deep submicron (UDSM) sign-off solution for IR drop and electromigration analysis of power distribution networks

News from Avant! Corporation (6 June 2001)

First hierarchical full-chip circuit simulator

Nassda Corp has announced version 1.3 of HSIM, which it describes as the EDA industry's first hierarchical full-chip circuit simulator

News from Nassda Corp (6 June 2001)

Integrated development package for Bluetooth SoCs

BlueForm from ARC Cores is a comprehensive package of hardware and software IP, development tools and application software for building Bluetooth SoC products based on the ARCtangent processor

News from ARC International (5 June 2001)

Cell, block and full-chip verification in one

New from Mentor Graphics, Calibre Interactive enables designers to perform block and cell physical verification from within layout environments such as Cadence Virtuoso Brochure available

News from Mentor Graphics UK (5 June 2001)

Design methodology bridges gap to fabrication

Monterey Design Systems describes System-Driven Physical Design as the first design methodology to enable physical chip implementation from system to GDSII tapeout of SoCs up to 100 million gates

News from Monterey Design Systems (5 June 2001)

Software simplifies comms line card development

The latest release of Cypress Semiconductor's popular Warp software design tools now includes support for its recently announced Programmable Serial Interface family of communications devices

News from Cypress Semiconductor (5 June 2001)

TSMC to support TetraMAX test pattern generation

TSMC is to support Synopsys' award winning TetraMAX automatic test pattern generation solution in its reference flow for all process technologies between 0.25 and 0.13 micron

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