Product category: Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial Team on 4 June 2001
TSMC to support
TetraMAX test pattern generation
TSMC is to support Synopsys' award winning TetraMAX automatic test pattern generation solution in its reference flow for all process technologies between 0.25 and 0.13 micron
In addition, TSMC has licensed TetraMAX for use in its Design Services Division, which provides chip implementation services to TSMC's customers and technical support to third-party design centres. This announcement demonstrates continued adoption of Synopsys test products by leading foundry and ASIC companies worldwide, and underscores the industry's recognition that advanced design-for-test (DFT) strategies are key to the successful manufacture of complex ICs.
This article was originally published on Electronicstalk on 4 June 2001 at 8.00am (UK)
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According to Fred Wang, director of the Design Service Division of TSMC, "TetraMAX clearly performed to expectations in our technical evaluation.
We developed the automatic test pattern generation module in the TSMC Reference Flow by implementing a scan-based test methodology using TetraMAX as the core tool.
TSMC Reference Flow users will benefit by saving tester time as a result of the vector compaction and higher test coverage over very large chips.
Ultimately, this will enable faster development of high quality, manufacturable devices".
As process geometries continue to shrink, allowing more transistors to be placed on silicon, the resulting devices' increased complexity may make them more expensive to test than to manufacture.
A strong DFT methodology implemented early in the design cycle will be mandatory to enable high quality, low cost testing in the manufacturing stage, avoiding cost overruns and time-to-market impacts.
"It is clear that TSMC recognises the benefits that our test methodology provides to the industry both today and in the future", said Bijan Kiani, vice president of marketing for Synopsys' Nanometer Analysis and Test Business Unit.
"Designers who consider test up front in the design cycle will experience a reduction in testing cost at the back end of the semiconductor process.
Right now, there is a real cost and time-to-market advantage to be gained by laying a strong DFT foundation into the design of next generation electronic devices".
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