First hierarchical full-chip circuit simulator

Nassda Corp has announced version 1.3 of HSIM, which it describes as the EDA industry's first hierarchical full-chip circuit simulator.

Nassda Corp has announced version 1.3 of HSIM, which it describes as the EDA industry's first hierarchical full-chip circuit simulator.

Aimed at designers of analogue, mixed-signal, memory and SoC integrated circuits, HSIM provides detailed circuit-level analysis of timing and power behaviour, and signal integrity effects.

This release delivers new analysis and device support along with enhanced interoperability with other design tools.

"HSIM version 1.3 further enhances the accuracy, performance, device model support and nanometer analysis we offer to designers", said Sang Wang, CEO of Nassda.

"Over 80 customers are using our technology in their design flows.

This commercial success has confirmed our hierarchical approach to circuit analysis for analogue, mixed-signal, memory and SoC designs.

This technology will become even more widely adopted by the design community as they move into geometries at 180nm and below".

HSIM solves the critical issue of analysing circuit behaviour while taking into account the electrical and parasitic effects of nanometer-scale silicon.

Before the availability of HSIM, design teams were unable to analyse these effects with a tool that had the speed, accuracy, and capacity that was needed.

In a recent benchmark, HSIM verified a 50 million transistor network processor in just over 13 hours on a 32bit workstation with 512Mbyte of RAM.

HSIM's ability to address critical verification issues is reflected in HSIM's dramatic rate of adoption by design teams throughout the world.

Nassda created HSIM to perform full-chip circuit simulation and analysis with accuracy within 1-2% of Spice, but at speeds three to four orders of magnitude faster than Spice.

HSIM uses a patent-pending hierarchical technology to deliver a capacity of over one billion transistors, and is targeted to both pre- and post-layout analysis of circuits.

HSIM now supports simulation of JFETs, found in communication designs, using the same model found in Spice simulators.

Another development for designers of high-speed systems is the ability to analyse signal integrity effects with a lossy transmission line model.

As well, the latest MOS device model from UC Berkeley for nanometer-scale devices, BSIM4, is now supported.

The existing silicon-on-insulator device model has been improved in accuracy by working closely with Nassda's customers.

With each new release, HSIM continues to incorporate the latest developments from industry and academic research.

HSIM version 1.3 provides enhanced support for the back-annotation of parasitic RC data in DSPF format, and MOS device geometry information including device size, parasitics and resistivity.

As they account for post-layout effects, back-annotation of DSPF and MOS device data is necessary for accurate analysis of signal integrity, and timing and power behaviour.

With version 1.3, HSIM now provides spectral analysis by means of the fast Fourier transform.

Performed interactively or after transient simulation, HSIM enables frequency analysis of communication circuits.

This new capability provides industry-standard windowing functions for conditioning the analysis data as needed by designers.

HSIM version 1.3 delivers improved interoperability with other design tools by providing an application programming interface for working with customers' internal waveform viewers.

The new release also provides a user modeling interface to integrate customer-proprietary device models.

HSIM Version 1.3 is now available, and is supported on workstations running Sun Solaris, HP-UX, Microsoft Windows NT/2000, and Linux operating systems.

US prices start at $85,000.

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