FPGA software simplifies I/O assignment

PinAhead technology provides the ability to assign interface I/O groups to I/O pins simply by dragging into a graphical representation of the FPGA.

Xilinx has released a new version of its PlanAhead hierarchical design and analysis design tool featuring the expanded functionality of Xilinx PinAhead technology.

Released earlier this year, PinAhead technology provides FPGA designers with the ability to assign interface I/O groups to I/O pins simply by dragging into a graphical representation of the FPGA.

PlanAhead 9.2 software further simplifies the complexities of managing the interface between the designer's target FPGA and the PCB with the ability to import and export I/O port information through VHDL or Verilog headers.

The 9.2 release of the company's award winning PlanAhead software also offers support for the company's latest low-cost Spartan-3A DSP platform FPGA, the industry's most cost-efficient devices optimised for wireless, video and consumer applications.

With the latest 9.2 release, PlanAhead software now supports the entire line of Xilinx Spartan-3 generation FPGAs.

"PlanAhead allows designers to divide a larger design up into smaller, more manageable blocks and focus efforts toward optimisation of each module, improving performance and quality of the entire design", says Salil Raje, Xilinx Director for Design Planning and Verification.

"Our latest 9.2 version allows designers to import and export I/O port information within their native HDL language, which further improves designer productivity".

PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout related changes that typically happen downstream.

Better user control of FPGA pinout early in the design process also offers significant improvements in performance, avoiding a nonoptimal pinout which causes further delays when trying to meet timing requirements.

By considering the data flow from PCB to FPGA die, optimal pinout configurations can be achieved quickly, thus reducing internal and external trace lengths and routing congestion.

During the pin planning process, PlanAhead 9.2 software allows users to better explore pinout information with extended reporting capabilities.

PlanAhead 9.2 software can now display more information about the I/O ports assigned to individual I/O banks.

Users can select an I/O Bank to view the values for VCCO, VREF and I/O standard.

Users can also display the number of I/O ports assigned to the I/O bank and the number of remaining available pins for assignment.

In addition, PlanAhead now provides an environment where users can better investigate individual clock regions by displaying information about the various I/O banks contained in each clock region.

Users can also create their own port list with a GUI interface or import a comma separated values (CSV) spreadsheet.

Through these multiple options, PlanAhead 9.2 software enables early decisions to be made, permitting PCB and FPGA designers to begin work much earlier with a much more realistic pinout configuration.

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