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News Release from: Virage Logic
Edited by the Electronicstalk Editorial Team on 26 July 2006

ASAP memory solidifies place in the SoC

Virage Logic's ASAP memory solidifies place in the SoC with incorporation into Ceva DSP platform

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Virage Logic Corporation, a pioneer in Silicon Aware IP and leading provider of semiconductor intellectual property (IP) platforms, and Ceva, the leading licensor of digital signal processor (DSP) cores, multimedia and storage platforms to the semiconductor industry, announced that Virage Logic's Area, Speed and Power (ASAP) Memory High-Speed (HS) memory IP has been adopted by Ceva for global use in its Ceva-XS based system platforms. Virage Logic's ASAP Memory HS is designed for high-performance applications, making it the perfect choice for the Ceva-XS platforms, including the Ceva-XS1200, which targets mobile multimedia applications such as high-end multimedia phones, personal media players (PMPs) and mobile TVs, and the Ceva-XS1102, which targets 3.5G/HSDPA handsets, WiMax/WiBro terminals and Smartphone applications. Ceva-XS is a family of low-power, highly integrated DSP system platforms designed to reduce development costs and time-to-market for customers designing next-generation DSP-powered devices.

Built around the industry-leading Ceva-X DSP cores, the Ceva-XS platforms use industry standard system buses, offering designers the ability to add their own hardware blocks or connect the DSP to other systems present on chip.

The ASAP Memory HS's high-performance architecture begins with the design of its bit cells, which are optimised for fast signal propagation, with the lowest possible bit-line coupling for very high stability.

Proprietary circuit design techniques, including high-speed sense amplifiers, fast clocking and fast bit-line recovery contribute to achieving the high speeds required by today's high-performance applications.

'Virage Logic's highly differentiated IP was chosen for its ability to help us maximise the performance of our Ceva-XS DSP Platforms,' said David Dahan, vice president of operations at Ceva.

'In turn, these performance advantages provide our customers with the ability to differentiate their products that target the multimedia, communications and consumer markets'.

'Ceva's decision to incorporate Virage Logic's ASAP Memory IP into their Ceva-XS system platforms underscores the speed and performance benefits that choosing the right physical IP provides to the overall performance of functional IP such as DSPs,' said Jim Ensell, senior vice president of marketing and business development for Virage Logic.

'We're very pleased to serve as Ceva's trusted IP partner'.

Increasingly complex System-on-Chips (SoCs) require greater amounts of memory, which present significant wafer yield issues.

Using Virage Logic's silicon-proven embedded memory IP, designers can integrate small, moderate or large amounts of on-chip memory to reduce overall system cost and size, while meeting time-to-market requirements.

The ASAP Memory HS product is suited for high-volume applications where high-speed, area-efficient memory implementation is a requirement.

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