Product category: Microprocessors, Microcontrollers and DSPs
News Release from: TSMC
Edited by the Electronicstalk Editorial Team on 20 July 2006

Collaboration cuts power in 65nm design

A design collaboration between TSMC and ARM on a 65nm low-power test chip has resulted in significant reductions in both dynamic and leakage power

Taiwan semiconductor manufacturing Company and ARM have announced that a design collaboration between TSMC and ARM on a 65nm low-power test chip resulted in significant reductions in both dynamic and leakage power. The two companies cited innovative low-power design techniques, which were key to successful results.

The year-long collaboration resulted in a 65nm test chip based on the ARM926EJ-S processor demonstrating advanced power-management technologies.

By applying dynamic voltage and frequency scaling techniques, the test chip provides the ability to operate at the lowest possible power level for each mode of operation.

In this case, the ARM test chip achieved a dynamic power reduction of over 50%.

Significantly, even on this TSMC 65LP low-leakage process, advanced power-gating technology further reduced standby leakage by a factor of 8x.

'Power efficiency is the most important challenge facing the semiconductor industry as mobile devices exploit advanced processes to deliver greater functionality and performance' said David Flynn, ARM Fellow.

'ARM and TSMC are partnering on 65 and 45nm technology development, and this project demonstrates the significant leakage and dynamic power reductions that we can achieve through close technical collaboration and implementation of fully functional silicon.

'One of TSMC's key differentiators is our insistence on proving our services, and those of our partners, in silicon before bringing them to the design community', said Ed Wan, Senior Director of Design Services Product Marketing.

'Our collaboration with ARM demonstrates beyond doubt that advanced process technologies, combined with innovative design techniques, and process-targeted libraries, could achieve distinct and significant power savings, which is absolutely vital to companies on the technological leading edge'.

The test chip incorporates low-power memory macros, level shifters, retention flip-flops, and isolation cells in the library, which is characterised for multiple voltages.

TSMC's power management collaboration with ARM is one component of a wide-ranging strategy to provide robust low-power capabilities.

New power management features developed through this test chip program include multicorner timing closure capability, which anticipates the timing impact of voltage scaling on the timing of library cells that offer different threshold voltages.

This technique recognises shifts in the critical path and earmarks them for timing analysis at any point in the design cycle.

Multi-threshold (MT) CMOS technology is implemented together with dynamic voltage and frequency scaling (DVFS) to reduce dynamic and standby (leakage) power for different operating conditions.

Design methodologies are demonstrated for power-gating cell wake-up/sleep control, power isolation and timing signoff for voltage islands.

ARM Intelligent Energy Manager (IEM) technology supports dynamic voltage and frequency scaling, and is now being extended to include leakage control using power gating and state retention under software control.

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