Product category: Memory Devices and Modules
News Release from: Toshiba Electronics Europe | Subject: Nine-layer MCP memories
Edited by the Electronicstalk Editorial Team on 23 January 2004
Novel package crams
more memory chips together
Toshiba has developed a multichip package (MCP) only 1.4mm high that stacks a total of nine layers of components
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The new package draws on Toshiba's latest advances in process and mounting technology - the ability to fabricate memory chips only 70um high, the thinnest chips yet developed for MCP application - to stack six memory chips with three spacers. The number of layers is a 50% improvement on the company's current state-of-the-art six-layer MCP and opens the way to more powerful and functional combinations of chips in a space-saving single package.
The new MCP can accommodate and combine a full range of memory chips, including SRAM, SDRAM, psuedo SRAM, NOR Flash memory and NAND Flash memory, and typical applications can achieve a total capacity as high as 776Mbit.
The flexibility offered by the MCP will support customers in creating powerful applications that enhance equipment performance while supporting circuit miniaturisation.
Toshiba will commercialise new MCP products based on the package in May this year.
Further reading
Microcontroller has SuperFlash code memory
Flash-based 16bit microcontroller for low-power portable applications
Compact microcontroller has many serial interfaces
A compact 8bit CMOS microcontroller combines 16kByte of SuperFlash memory with a large number of serial interfaces and new analogue IP blocks to detect low voltages and perform power on reset
Toshiba's latest process technology has realised a chip for MCP application that is only 70um high, a full 15um thinner than the company's present 85um chips.
This, and improved mounting technology, now allows the company to stack and wire nine layers, including six layers of memory chips, in the same 1.4mm high package that currently supports six-layer MCP.
The new MCP also optimises data transfers between the CPU and the MCP through adoption of a "triple-databus system" that matches chip type to the right kind of bus.
A high-speed bus supports SDRAM and NOR, a middle-speed bus SRAM and NOR, and a dedicated bus supports NAND.
At 11 x 14 x 1.4mm, Toshiba's new MCP is small, slim and powerful.
It will bring higher capacity, denser memory capabilities to digital mobile equipment, including mobile phones with camera, and the ability to configure the most appropriate chips for specific applications will assure the delivery of optimised solutions and minimised power consumption.
The May introduction of the new nine-layer MCP is expected to reinforce Toshiba's leadership in what is fast becoming the device of choice for advanced mobile phones and other personal digital equipment.
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