Product category: Microprocessors, Microcontrollers and DSPs
News Release from: Toshiba Electronics Europe | Subject: MeP architecture
Edited by the Electronicstalk Editorial Team on 24 February 2003
Coprocessor speeds image recognition SoC
Toshiba has developed a three-way VLIW (very large instruction word) coprocessor extension based on the company's open and configurable/extensible MeP media embedded processor architecture
This powerful VLIW coprocessor has been developed using Toshiba's MPI media embedded processor integrator design and development system and implemented in a customised image-recognition SoC. The development of the new VLIW coprocessor module represents the next stage of Toshiba's MeP architecture evolution.
This article was originally published on Electronicstalk on 24 February 2003 at 8.00am (UK)
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A number of SoC solutions including audio codecs, MPEG2 encoders and decoders and MPEG4 codecs have been developed or are now under development.
The new VLIW coprocessor extension and a MeP core form a MeP module that has been integrated, along with peripheral modules, into an image recognition SoC.
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This SoC is fabricated in Toshiba's TC280, 0.13um CMOS process and provides the image recognition and video processing functionality required by next generation automotive surveillance systems.
Toshiba's MeP core supports a tightly coupled VLIW coprocessor.
In the image recognition SoC, the MeP module that incorporates the VLIW extension has two processing modes, VLIW-mode and core-mode.
In the VLIW mode, a 64bit, fixed length VLIW instruction is issued every cycle.
Then the core processor and the VLIW coprocessor jointly execute this code.
In core-mode, a 16 or 32bit variable length instruction is issued every cycle and is executed only by the core processor.
To speed the development of the new three-way VLIW coprocessor extension, Toshiba used its integrated MPI design and development system.
MPI includes development tools - such as a compiler and a simulator - that can be customised to a given processor configuration.
In addition, MPI creates synthesisable RTL based on the configuration, and generates verification programs for RTL design.
One of the key MPI features is the Arcadia tool.
Arcadia automatically generates and customises development tools for a VLIW coprocessor from a user-defined specification, containing key architecture information such as VLIW type (two- or three-way), register information, and instruction definitions.
When the architecture changes, all tools are regenerated from the new specification.
This enables users to rapidly evaluate coprocessor prototypes with different architectures.
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