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Product category: Analogue and Mixed Signal ICs
News Release from: Texas Instruments (April 2001-March 2006)
Edited by the Electronicstalk Editorial Team on 24 March 2004

65nm process to start sampling in 2005

Maintaining a two-year cycle between manufacturing technology generations, Texas Instruments has revealed details of its 65nm semiconductor manufacturing process technology.

Maintaining a two-year cycle between manufacturing technology generations, Texas Instruments has revealed details of its 65nm semiconductor manufacturing process technology that is expected to shrink equivalent 90nm designs by half and boost transistor performance 40% TI's new technology can also reduce leakage power from idle transistors by a factor of 1000 while simultaneously integrating hundreds of millions of transistors that support both analogue and digital functions in SoC configurations

The company has 4Mbit SRAM memory test arrays functional today, and plans to sample a wireless product built with the new process in the first quarter of 2005.

"TI's 65nm CMOS process doubles the transistor density over our qualified 90nm production process and positions Texas Instruments for a leadership role in delivering the benefits of 65nm to customers early next year", said Hans Stork, Chief Technology Officer, Texas Instruments.

"Along with the tremendous increase in functionality TI will offer at 65nm with highly integrated SoC designs, we are taking significant steps to lead the industry in managing the power those designs consume".