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Product category: Standard Logic Devices
News Release from: Texas Instruments (April 2001-March 2006) | Subject: 90nm process
Edited by the Electronicstalk Editorial Team on 7 February 2002

Process technology takes
logic down to 90nm

Texas Instruments has revealed details of its next generation 90nm (or 0.09-micron) logic manufacturing process technology featuring transistors as small as 37nm

With the ability to pack over 400 million transistors on a single chip, TI's technology will drive cost-effective SoC solutions with unprecedented levels of performance and power savings for TI DSP, high-performance ASICs and Sun Microsystems designed UltraSPARC processor products. It is the combination of copper, low-k dielectric material, the industry's highest SRAM density and TI's 37nm transistor that will advance TI's leading edge DSP and Sun Microsystems' UltraSPARC processor products in the 90nm process.

'TI's advanced process technology keeps the UltraSPARC architecture at the forefront of processor performance', said David Yen, vice president and general manager, Processor Products Group, Sun Microsystems.

'TI innovations in process, transistor, interconnect and packaging demonstrate TI's leadership in technology and help both TI and Sun stay competitive in the markets they serve.

We look forward to a continued relationship with TI for our leading edge processor products which leverages TI's excellence in silicon process'.

Previous process generations typically use a single pair of CMOS transistors optimised to support all the circuit functions on a chip.

However, TI's 90nm process makes it possible to use a collection of transistors that are 'tuned' for different functions on a single chip to meet a variety of performance, density and power consumption requirements.

This is done through adjustments to the transistors' gate length, threshold voltage, gate oxide thickness or bias conditions.

The result is that transistors with the highest performance can be used in performance critical functions such as signal processing, whereas transistors with lower power consumption can be used to support functions with more stringent active and standby power requirements.

TI expects this capability to reduce system power by two to three times in future products.

TI ASIC libraries will support 1.8, 2.5 and 3.3V I/O interfaces, and analogueue/mixed-signal macros using optimised analogueue transistors and high-k dielectric capacitors, a first for production logic processes.

For SoC designs, especially those targeted toward portable systems where silicon area is a premium, integrating these analogueue functions can enable lighter-weight, less expensive, more mobile applications.

These integration capabilities also will enable cost and power reductions in high performance applications such as broadband, where single-chip DSL routers that combine the analogueue line driver, DSL transceiver and network processors become reality.

TI continues to offer extremely dense embedded SRAM in the 90nm process.

Specifically, the 90nm process includes 6T SRAM that enable densities of up to nearly 700Kbit/mm2, the highest density offered in the industry.

This capability is enabled with no process adders over standard CMOS in the ASIC library.

A power-optimised version with the same densities will be available in the high performance ASIC library.

'TI is unique in its ability to combine its DSPs, microcontrollers, memory, logic, analogueue and RF on a single chip', said Dr Yoshi Nishi, senior vice president, Research and Development, Texas Instruments.

'TI's 90nm process will allow the company to drive future generations of DSPs and UltraSPARC processors into multi-gigahertz operation, but also the integration and circuit optimisation required to match the device architecture with its target application area'.

TI will offer several optimised 90nm process flows to meet the unique needs of end products or applications, including performance, power dissipation, integration, on-chip multi-processing or lower cost.

Two of these flows include a collection of optimised DSP and microcontroller cores for both high-performance and low-power DSP-based end equipments.

The flow, which supports TI's high performance ASIC library, called SR50, exceeds integration and performance requirements of communication infrastructure products, for instance.

The second option, called GS50, is a low-leakage flow that will allow for lower power operation, longer battery life and less heat generation.

This flow is optimised for devices such as 2.5 or 3G wireless phones, digital cameras and Internet audio players.

The last flow is a high-performance computing products flow that Sun Microsystems plans to target for next generation UltraSPARC processor-based workstations and servers.

Through increased transistor performance and an optimised metal interconnect system, TI estimates that UltraSPARC processor performance will double over today's solutions.

Devices will also achieve considerable power savings by migrating to 90nm technology, enabling higher density system designs for Sun products.

The 90nm process includes up to nine layers of copper interconnect integrated with a low-k dielectric, organo-silicate glass (OSG), that has a k (dielectric constant) of 2.8.

TI has extended its history as an innovator in gate dielectric materials, as this process is the 3rd generation of TI's technology to use a plasma nitrided oxide (PNO) for the core transistors, which will be scaled to 1.3nm for the first time.

PNO maintains the transistors' high level of reliability, minimises gate leakage and allows TI's 90nm technology to meet its performance benchmarks.

TI's 90nm process is being developed for both 200 and 300mm production, with production expected in mid-2003.

TI's low power ASIC library is expected to be available at the end of the first quarter, with the high-performance library planned to follow in 3Q02.

'TI's 90nm technology will allow TI to continue providing customers with cost-effective solutions with the highest levels of performance, power efficiency and system level integration' summarised Dr Nishi.

'This announcement is another extension of TI's track record in being at the forefront of process technology research, development and implementation'.

(This was Electronicstalk's Top Story on 6 February 2002)

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