Design upgrade maximises IC throughput

The combination of increasing IC complexity and shrinking semiconductor features is driving increased demand for design and manufacturing-related compute resources.

Synopsys has released a multicore initiative to deploy parallel, threaded and other optimised compute technologies across its Discovery Verification and Galaxy Design platforms and design for manufacturing (DFM) solutions.

The initiative aims to enable integrated circuit (IC) design companies to easily maximise the throughput of their multicore compute infrastructure to reduce time-to-results (TTR).

This initiative builds on Synopsys' multiprocessor and network-distributed electronic design automation (EDA) solutions, including the VCS functional verification solution with native testbench technology for compute farms and the Proteus lithography solution, which offers near-linear scalability.

Additional multicore-enabled solutions will be delivered throughout 2008.

The combination of increasing IC complexity and shrinking semiconductor features is driving increased demand for design and manufacturing-related compute resources.

Synopsys' initiative addresses this demand by deploying advanced multicore software and optimised information technology (IT) solutions that can deliver productivity increases.

Galaxy Design Platform is the industry's most widely used implementation solution, including Synopsys' Design Compiler RTL synthesis solution; IC Compiler comprehensive place and route solution; the PrimeTime suite for sign-off; Star-RCXT parasitic extraction; TetraMAX automatic test pattern generation (ATPG) and Hercules physical verification solutions.

The Discovery Verification Platform is Synopsys' system to silicon verification solution, including System Studio for algorithm design and analysis; VCS functional verification; and HSPICE, NanoSim and HSIM circuit simulation solutions.

The DFM solution includes the Proteus OPC solution for mask synthesis; CATS mask data preparation; and the Sentaurus TCAD tool suite for semiconductor process and device modeling.

"Intel and Synopsys have a long history of engineering collaboration in the area of scalable compute infrastructure and advanced software engineering techniques", said Elwood Coslett, Director of Platform and Design Capability Engineering at Intel.

"Most recently, we have jointly worked to deploy and use the Intel Software Development Products (including the Intel Compilers, VTune Performance Analyser, Intel Threading Analysis Tools, Intel Performance Libraries and Intel Threading Building Blocks) to Synopsys' global software engineering community to enable rapid development of multicore processor based solutions".

"We are now in an environment where the cost to house, power and cool the IT infrastructure is greater than the capital acquisition cost", said John Chilton, Senior Vice President of Marketing and Business Development at Synopsys.

"Simply throwing more hardware and data centres at the problem is neither economically viable nor environmentally sustainable".

"In order to improve overall design time-to-results, EDA tools must increase throughput but also be deployed on optimised IT solutions specifically addressing the issues facing complex design-to-manufacturing processes".

"With the multicore initiative, Synopsys is attacking these challenges on all fronts to accelerate design throughput for our customers".

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