Compiler aids SoC differentiation: News from Synopsys

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Toshiba Corporation has used the Synopsys IC Compiler next-generation physical implementation solution to successfully tape out its next-generation TC90515XBG home digital network chip. Compared with its predecessor, the TC90515XBG delivers higher performance and increased functionality with reduced die-size and lower power consumption. The ability to use IC Compiler to concurrently optimise the design across all five of its operating modes was a critical factor in Toshiba's ability to meet its aggressive performance goals.

IC Compiler was also able to significantly speed Toshiba's time-to-results due to its unified user environment for all design steps from prototype floorplanning to final chip finishing.

Toshiba was able to further reduce the cost of the design by adopting Synopsys' DFT Max adaptive scan technology to reduce chip testing time.

'We were impressed by our early results with IC Compiler and decided to use it for the complete physical design of the TC90515XBG', said Dr Tohru Furuyama, General Manager of the Centre for Semiconductor Research and Development, Toshiba Corporation.

'We found that IC Compiler met our expectations, allowing us to design a highly differentiated SoC while meeting our delivery schedule'.

Toshiba's TC90515XBG is a 90nm high-performance wireless chip for consumer networks.

It has a dual MeP core architecture that supports all IEEE802.11 wireless LAN standards; MPEG-2 TS, PCI, I2C and IR (Infra-Red) interfaces; and content protection with DTCP-IP.

The chip has two functional modes at 200 and 80MHz and three test modes, all of which were optimised concurrently by IC Compiler to give significant improvements in hold-time fixing and reduced margin.

IC Compiler also helped reduce the chip's leakage power by optimising the tradeoff between high-speed and low-power cells.

'IC Compiler and the Galaxy platform allowed us to significantly accelerate our time to results', said Takashi Yoshimori, Technology Executive of SoC Design, Semiconductor Company, Toshiba Corporation.

'IC Compiler gave our designers a comprehensive solution for physical design with one set of libraries and constraints, a single-user environment, and support for physical test and power optimisation'.

'In addition, we found the tight correlation to sign-off with PrimeTime SI to be a key contributor to faster design closure'.

Toshiba found that new optimisations within IC Compiler, combined with extensive analysis capabilities, were easy to use and shortened their time to results.

IC Compiler's completeness allowed Toshiba to use the same tool for all physical implementation steps from initial prototyping to final finishing.

Toshiba was able to achieve over 80% area utilisation, power-network voltage drop of less than 25mV and over 80% low-leakage (high Vt) cells for improved leakage-power dissipation.

'Toshiba has long been a key customer and an early adopter of our most advanced technologies, such as IC Compiler and DFT Max'.

'The results achieved with the TC90515XBG chip are clear evidence of the success of our close collaboration', said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.

'We value Toshiba's input in guiding our products and look forward to working with them on future advanced designs'.

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