Product category: Intellectual Property Cores
News Release from: Synopsys | Subject: TSMC Nexsys IP libraries
Edited by the Electronicstalk Editorial Team on 22 May 2006
Library lends IP
support to 65nm process
TSMC has appointed Synopsys to distribute its production-ready, silicon-validated 65nm Nexsys standard cell libraries, I/Os and memory compilers through Synopsys' DesignWare IP library
TSMC developed the libraries in close relationship with their process development teams to ensure conformance to TSMC's design-for-manufacturing rules. TSMC validated the libraries through the TSMC-9000 programme to meet their rigorous library quality criteria. TSMC and Synopsys also worked together to validate that the Nexsys libraries provide full support for the TSMC Reference Flow 6.0 within Synopsys Galaxy Design and Discovery Verification Platform.
This article was originally published on Electronicstalk on 22 May 2006 at 8.00am (UK)
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'We worked closely with Synopsys to optimise, distribute and support our standard cells, I/Os and memory compilers', said Ed Wan, Senior Director of Design Service Marketing at TSMC.
'It's important for our customers to get early access to fully validated IP for our most advanced processes, which accelerates the adoption of 65nm designs'.
TSMC Nexsys standard cell libraries offer a complete set of high-performance, high-density cells and include multiple voltage thresholds to enable power and speed tradeoffs.
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The Nexsys libraries also enable low power design and mitigating power leakage by supporting power gating and voltage scaling design implementations.
TSMC's I/Os offer unique features such as circuit-under-pad, flip-chip support and staggered or linear bonding within one library.
TSMC's memory compilers, available for TSMC's 65nm low power (LP) process, are optimised for low dynamic and leakage power.
They include a single port SRAM with and without redundancy, dual port SRAM, a single-port and two-port register file, and a ROM compiler.
'This significant expansion to our existing library distribution relationship with TSMC gives DesignWare Library users easy access to high-quality IP for the most advanced silicon processes', said Guri Stark, Vice President of Marketing for the Solutions Group at Synopsys.
'The TSMC Nexsys libraries are a key element in our broad portfolio of silicon-proven IP.
Working with TSMC illustrates our commitment to provide essential IP to engineering teams worldwide for the development of their leading-edge SoC designs'.
The TSMC Nexsys standard cell libraries and I/Os for the 65LP processes are available immediately through the DesignWare Library at no additional cost to current licensees.
TSMC's Nexsys memory compilers for TSMC 65LP and TSMC 90LP are licensed separately and available immediately through Synopsys.
TSMC's Nexsys standard cell libraries and I/Os for 90nm, 0.13um and 0.15um process nodes are also available through the DesignWare Library at no additional cost to current licensees.
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