Product category: Design and Development Software
News Release from: Synopsys | Subject: SystemVerilog support
Edited by the Electronicstalk Editorial Team on 22 March 2006
SystemVerilog support covers full design
chain
Synopsys now supports the SystemVerilog language throughout its suite of design and verification products, extending its SystemVerilog leadership and establishing another industry-first achievement.
Synopsys now supports the SystemVerilog language throughout its suite of design and verification products, extending its SystemVerilog leadership and establishing another industry-first achievement Important elements in Synopsys' comprehensive SystemVerilog design and verification flow were made available today as the company introduced SystemVerilog verification IP support for its VCS Verification Library in a separate announcement and announced a new native SystemVerilog parser in its Formality equivalence checker
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Design and verification engineers who use logic synthesis, simulation, verification IP, testbench automation, RTL checking, formal analysis and equivalence checking tools can now benefit from the faster performance, improved productivity and increased predictability advantages of using the IEEE Std 1800-2005 SystemVerilog standard, the industry's only electronic design and verification language.
More than 150 companies are using Synopsys' SystemVerilog solutions today to design and verify the advanced systems-on-chips (SoCs) that are used in cutting-edge consumer electronics, networking and telecommunications equipment and computer systems.
Design engineers are able to leverage SystemVerilog to express their highly-complex designs more succinctly and accurately, capture critical design attributes with assertions and develop advanced coverage-driven, constrained-random