Product category: Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial Team on 27 January 2006
Japanese companies add support for
SystemVerilog
The Verification Methodology Manual for SystemVerilog has been endorsed by the Semiconductor Technology Academic Research Centre and major electronics companies in Japan.
The Verification Methodology Manual (VMM) for SystemVerilog has been endorsed by the Semiconductor Technology Academic Research Centre (STARC) and major electronics companies in Japan as a reference to develop advanced verification environments based on the IEEE standard SystemVerilog language The Japanese-language edition of the manual will be published by CQ Publishing in Japan
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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