Product category: Design and Development Software
News Release from: Synopsys | Subject: Galaxy
Edited by the Electronicstalk Editorial Team on 11 September 2003
Design platform speeds
network processor tape out
Agere Systems has used Synopsys' Galaxy design platform to tape out its 5G APP550 network processor in a 0.13-micron process
Agere Systems has used Synopsys' Galaxy design platform - employing Physical Compiler physical synthesis, Astro physical design, Star-RCXT parasitic extraction and Jupiter design planning solutions - to tape out the 5G APP550 network processor in a 0.13-micron process. "Agere needed a predictable, proven design tool with advanced timing closure support for our network processor", said Bill Burroughs, Technical Manager within the Multiservice Networking Division of Agere Systems.
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"By using the physical implementation tools in the Galaxy design platform, we met our performance target with a significant improvement in the timing-closure interval.
In addition, Synopsys gave us excellent support during the design process".
Agere's ASIC design flow is built around Physical Compiler for achieving rapid timing closure from a register transfer level (RTL) description to placed gates.
Further reading
Reference flow takes design platform onboard
The latest TSMC reference flow incorporates unique features and innovations of Synopsys' Galaxy design platform for designs at 130nm, 90nm and below
Agere engineers used Physical Compiler's synthesis and placement together to obtain a timing-clean result in a short and predictable time.
The APP550 network processor was designed using Agere's SoC design flow, which is built around Astro for physical implementation.
The tight integration between Physical Compiler and Astro's signal integrity-aware routing allowed Agere to complete the network processor on schedule and produce parts working to specification.
Several first-tier global computing and communications OEMs have already chosen the APP550 for their next-generation multiservice networking equipment.
The Agere APP500 family of products are highly integrated network processors that have robust classification, AAL5 segmentation and reassembly (SAR), integrated world-class traffic management for multiservice applications, and on-chip Ethernet MACs.
"Agere's design success with its network processor and ASICs demonstrates why the Galaxy design platform is at the heart of physical design for today's highly sophisticated designs", said Antun Domic, Senior Vice President and General Manager of the Implementation Group at Synopsys.
"By providing common libraries, delay calculation and constraints with consistent timing, the Galaxy design platform provides fast and predictable turn-around time from design-to-results".
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