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Product category: Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial Team on 7 March 2002

Synopsys and STMicroelectronics
to cut test costs

Synopsys has embarked on a two-year partnership with STMicroelectronics focused on creating new methodologies and technologies to reduce manufacturing test development cost and effort

Synopsys has embarked on a two-year partnership with STMicroelectronics focused on creating new methodologies and technologies to reduce manufacturing test development cost and effort while simultaneously improving test quality. This new alliance is to develop and deploy advanced manufacturing test solutions innovated by Synopsys and STMicroelectronics that solve test challenges at reduced costs, and provide turnaround time and time to market advantages for complex SoC devices.

"ST is an industry leader in the creation of state-of-the-art SoCs for consumers, including telecommunications, computer, automotive, and video applications.

We set extremely high quality standards for all of our products", said Aldo Romano, corporate vice president and general manager of the Telecommunications, Peripherals and Audio and Automotive (TPA) Groups, STMicroelectronics.

"The rapidly increasing complexity of ST's products, coupled with our stringent manufacturing testability requirements, leads us to believe that manufacturing test challenges and costs will become a critical bottleneck if we don't take early strategic action.

Partnering with Synopsys is a key part of the ST strategy to attack test challenges with a disciplined, unified approach, tightly linking design with manufacturing test.

We see this as a long-term solution to reduce the risk of unacceptable growth in test costs".

"As the leader in design and DFT automation, Synopsys provides the foundation for test in design flows.

Therefore, it is important for us to partner with the leaders in SoC design and production to help our customers achieve the goal of seamless DFT closure from RTL to packaged parts", said Aart de Geus, chairman and CEO of Synopsys.

"Our manufacturing test alliance with ST is a prime example of the synergies that this type of partnership can provide: ST gives us an early and complete view of their production processes and technology requirements, and we tailor our DFT technology roadmap to meet their needs.

At the same time, we work to advance the state of the art for our broader customer base".

This new alliance will expand on the accomplishments of an earlier ST/Synopsys test partnership, enabling design-for-test (DFT) closure for SoC design flows by adding two major objectives: First, the alliance will aim to optimise ST's design-to-manufacturing test flows to greatly improve turnaround time and time to market; and second, it will strive to enable ST to dramatically reduce its manufacturing test costs.

To accomplish these objectives, ST brings its experience as an integrated device manufacturer with a comprehensive view of SoC design and manufacturing, and Synopsys brings its innovations in DFT technology and expertise in unifying design and manufacturing test.

The key to successfully meeting these objectives is to create new links between the DFT and automated test equipment environments.

By leveraging automation and standard interfaces using the IEEE P1450.6 Core Test Language, these new links will greatly speed up ST's SoC test program development, production debug and diagnostic flows.

In addition, by enabling ST designers to deploy innovative Synopsys technologies that optimise DFT structures for specific manufacturing requirements, these links enable potentially dramatic reductions in ST's manufacturing test costs, with no impact on the quality of test.

"ST has worked with Synopsys on many successful technology partnerships, and this new alliance is particularly noteworthy because its goal is to directly reduce ST's manufacturing test cost and effort, while optimising test quality", said Joel Monnier, corporate vice-president and director of Central R and D, STMicroelectronics.

"This goal is very challenging, as it requires close collaboration among ST's SoC design and manufacturing groups, our EDA test supplier Synopsys, as well as our ATE providers.

We believe that this innovative alliance with Synopsys will be the fastest and most effective route to achieve ST's corporate objectives in lowering our overall cost of test".

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