Product category: Design and Development Software
News Release from: Solido Design Automation | Subject: SolidoStat
Edited by the Electronicstalk Editorial Team on 17 September 2007
Software cuts parametric yield loss
SolidoStat is a Stat tool for transistor-level statistical design and verification.
Solido Design Automation has released software for the semiconductor industry that solves the problem of preventable parametric yield loss in integrated circuit design SolidoStat is a Stat tool for transistor-level statistical design and verification
This article was originally published on Electronicstalk on 16 Jan 2006 at 8.00am (UK)
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According to Amit Gupta, Solido's cofounder and CEO, as semiconductor process technologies and supply voltages shrink, microscopic local and global statistical variations adversely impact