Reconfigurable processors target soft radios: News from Silicon Hive

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Silicon Hive, a new business entity created through the Technology Incubator Programme of Royal Philips Electronics, has launched a comprehensive new hardware/software codesign solution that allows SoC designers to leverage the performance advantage of reconfigurable computing - a breakthrough technology that pushes programmability and performance far beyond the limits of current DSP-based solutions. The Bresca and Avispa embedded processor cores and associated software libraries from Silicon Hive are targeted at applications in software-defined radio. In one consumer-end application, the automotive radio market, these cores enable one low-cost programmable integrated circuit (IC) to replace the several IC modules that would otherwise be required for each radio broadcast format supported in the receiver.

This single software-defined radio IC could be configured to receive digital satellite radio broadcast services, in-band on-channel (IBOC), digital audio broadcast (DAB), or even support GPS features.

Additionally, in the wireless LAN market, a single low-cost IC may be programmed with multiple wireless LAN standards, or even upgraded with new designs that improve performance or add new features.

These new reconfigurable computing solutions from Silicon Hive combine the flexibility of processor driven systems with the execution speed and low power consumption of ASICs.

As a result, they can achieve the sustained data rates required to demodulate a radio receiver's digitised IF frequency (typically a frequency of several megahertz).

This makes it possible to adapt the receiver to virtually any broadcast standard simply by changing software.

In addition to IF signal processing, the Bresca and Avispa cores can also perform all the required baseband and source processing in a receiver.

Designed for integration into low-cost SoC solutions, they not only meet the cost, performance, flexibility and time-to-market requirements of high-volume consumer applications.

Their programmability also enables OEMs to protect valuable application IP.

"Developing a totally new computer architecture to perform tasks that even the latest DSPs are simply not capable of handling is not enough", said Geoff Burns, Product Development Manager at Silicon Hive.

"You also need to provide a hardware and software development environment that allows designers to start using your solutions straight away, which is what we are releasing today".

The Bresca core is a reconfigurable accelerator designed to provide the very high guaranteed throughput rates required for high-speed streaming data.

The Avispa is a reconfigurable accelerator targeted for block processing tasks such as transforms and frequency-domain equalisers.

Both are soft cores that can be integrated alongside conventional processors, such as ARM and MIPS cores, into SoCs based on any available semiconductor process technology and industry-standard hardware design flows.

The Bresca and Avispa cores are fully ANSI C programmable, and are supplied with a comprehensive library of precompiled software modules that developers can assemble into software-defined radio solutions.

The performance of both the cores and software libraries has been fully qualified for current digital satellite and digital terrestrial broadcast systems.

An ANSI C compiler that will allow users to develop their own library components is currently being readied for release.

"The beauty of our reconfigurable cores is that you can instantly switch a low-cost receiver platform between different modulation schemes such as OFDM (orthogonal frequency division multiplexing) and QPSK (quadrature phase-shift keying) simply by context switching the software, making a truly universal satellite/terrestrial broadcast receiver possible", said Burns.

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Reconfigurable processors target soft radios

A comprehensive new hardware/software codesign solution allows SoC designers to leverage the performance advantage of reconfigurable computing.