Codesign package moves to next level: News from Summit Design

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Summit Design has expanded its Visual ESC package - a complete hardware/software verification environment using the first true SystemC platform - to support the MIPS64 5K core family and verification IP from Denali Software. A part of Summit's innovative Visual Elite functional modelling, design and verification environment, Visual ESC serves as a high-performance HW/SW coverification platform with fast integrated instruction set simulators (ISS) for target architectures. This unique platform leverages the performance and abstraction provided by SystemC.

The greatly expanded Visual ESC package provides customers with an integrated ISS that is tightly linked with vendor-specific software environment tools to drive platform-based design.

Most of the major components are all integrated in a powerful SystemC environment with built-in verification capabilities.

Visual ESC allows interface of the ISS at a signal-level, or at a transaction-level for higher performance.

In addition, it provides fully synchronised, hardware and software debugging and visibility.

Users are allowed to plug-and-play in their desired architecture with a minimum investment and maximum value from all of the SystemC language advantages, such as performance and abstraction.

This solution will substantially reduce the adoption cycle for those who want to start with SystemC.

Already in use by customers, Summit's Visual ESC package integrates the MIPSsim ISS and is compatible with the MIPS software toolkit, which includes the MIPS SDE software tool chain for the 5K processor family.

Summit's Visual ESC package also supports SystemC interfaces with pin-level or bus transaction-level plug-ins.

HDL modules can also be linked for simulation.

"Summit Design's ESL solution is a great tool for facilitating the adoption and verification of our processors, and it offers high-performance simulation linked with optimised software tools", said Russ Bell, Vice President of Marketing at MIPS Technologies.

"With new submicron technologies, Summit's powerful platform provides great value for our customers in their efforts to shorten verification investment and reduce silicon power and cost".

Summit has integrated Denali's MMAV and PureSpec verification IP platforms with Summit's Visual ESC for external memory interfaces and PCI Express designs.

"Summit, with its Visual ESC, enables our customer base to fully utilise our verification IP in a high-performance SystemC platform", said Kevin Silver, Vice President of Marketing with Denali.

"This gives our customers the ability to upgrade seamlessly to a higher level of abstraction while also benefiting from advanced verification and analysis - and that is a value that our users are sure to enjoy".

Today's Visual ESC offers more variety of architectures and is the only one that supports hardware description languages (HDLs) as well as SystemC.

The graphical constructs make it easier for hardware engineers to design in these various models.

"A SystemC platform-based design for integrated HW/SW SoC is the best showcase for ESL".

"The value and ROI are substantial", said Rami Rachamim, Director of Marketing at Summit.

"The new agreement and co-operation we have now with the leading IP and model providers enable us to offer customers a seamlessly integrated platform".

"Our target users now have access to a large set of the needed components in their target architecture, enabling them to run verification and analysis without changing tools or design flows".

The Visual Elite ESC package is available now, with prices beginning at US $20,000.

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Codesign package moves to next level

Summit Design has expanded its Visual ESC package to support the MIPS64 5K core family and verification IP from Denali Software.