Soitec produces silicon-on-insulator substrates

Soitec has announced volume production of its new generation of high-resistivity (HR) silicon-on-insulator (SOI) substrates to serve the mobile phone and wifi markets.

Soitec has fine tuned its HR-SOI process to stabilise the base-wafer resistivity in order to meet all cellular electrical specifications.

Soitec's Smart Cut technology is used to integrate a high-resistivity base wafer, enabling low signal absorption below the oxide.

This high-resistivity option for SOI wafers enables chip designers to reach high levels of RF and mixed-signal integration, which will free up space for the RF functions by a factor of 10 on the board.

High-resistivity handle layers can also be combined with advanced SOI technologies that leverage a very thin top layer of silicon.

Such wafers are excellent candidates for combining wireless functionality with lower power and higher speed logic on a single chip using a standard SOI CMOS process.

Manufactured in 200mm, Soitec's HR SOI substrates offer more than 1kOhm/cm resistivity, available in any custom silicon and box thickness.

The company also offers HR SOI substrates in 300mm for the system-on-chip market working at the 90nm node and below.

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