Product category: Design and Development Software
News Release from: Real Intent | Subject: Verix
Edited by the Electronicstalk Editorial Team on 31 May 2002
Verification system crosses clock domains
Real Intent has added formal clock intent verification to its flagship electronic design verification system Verix
Assertion-based formal clock intent verification analyses and exhaustively verifies the stability and correctness of data transfer between clock domains. According to Dr Prakash Narain, Real Intent's President and CEO: "Verix now brings the exhaustive confidence of assertion-driven formal verification to verify the stability and correctness of data transfer between clock domains".
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Clock Intent verification automatically identifies the clock domains and the hazards for signals crossing those domains.
It further advises the designer about appropriate assertions to formally verify the data transfer.
All the user needs to supply is the RTL and to identify clocks.
The Verix clock intent verifier looks at the RTL design description and automatically identifies the clock domains within the design and the signals crossing the clock domains.
In addition, it identifies the absence or presence of synchronizers at the clock domain boundaries, and determines Verix assertions that can exhaustively verify the data transfer stability across the clock domain boundaries.
Further reading
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All-new new approach to CDC verification is engineered to verify that data traversing asynchronous clock domains on ASIC, SoC or FPGA devices is received reliably
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The challenge of safe data transfer between clock domains is a common and difficult problem facing designers of SoCs and ASICs where data producers and data consumers run at different clock rates.
The problem is caused at the systems level when multiple clock domains exist between high-speed processors and lower speed peripherals and in modern communication systems with multiple data sources running at different asynchronous clock rates.
Designers employ a variety of clocking schemes to generate these synchronous and asynchronous clocks.
Then, the designer must verify reliable data transfer for all possible combination of conditions.
The exhaustive nature of assertion-driven formal verification is ideally suited to verify this kind of problem.
Typically, it is difficult to model and verify these problems in simulation, as the development of a test bench that exercises every possible combination of signals is a very daunting task.
Verix is Real Intent's pioneering assertion-driven formal verification system that verifies that a design is free from a large class of errors early in the design cycle, prior to simulation and synthesis.
Verix features a number of formal verification innovations including: automatic checks, scalable hierarchical verification, in-line assertions and automatic generation of simulation checker from formal assertions.
Verix speeds the design of high-end semiconductors and systems-on-chip by formally verifying the design as the RTL is created.
In March, Real Intent and Co-Design announced the joint donation of their Design Assertion Subset (DAS) to Accellera.
Dr Narain noted, "Real Intent is committed to Accellera's efforts for the standardization of assertions.
Our active participation and support of Accellera's SystemVerilog standardisation efforts underlines our mission to bring a standard verification methodology to our customers".
Verix pricing starts at $50,000/year.
The Verix clock intent verification capability is available on Sun, HP and Linux platforms and supports both Verilog and VHDL designs.
(This was Electronicstalk's Top Story on 31 May 2002)
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