Product category: Microprocessors, Microcontrollers and DSPs
News Release from: Oki Electric
Edited by the Electronicstalk Editorial Team on 08 July 2005
Mixed-mode simulation aids ESD immunity
Oki Electric has developed a novel electrostatic discharge (ESD) protection circuit design technique it claims can reduce ESD protection circuit design time by one-third.
Oki Electric has developed a novel electrostatic discharge (ESD) protection circuit design technique it claims can reduce ESD protection circuit design time by one-third This is the world's first ESD protection design methodology using mixed-mode simulation, offering both device and circuit simulation functions
This article was originally published on Electronicstalk on 10 Apr 2002 at 8.00am (UK)
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ESD immunity has declined alongside rapid improvements in device performance and ever-shrinking design scales.
Attempts to resolve this degradation of ESD immunity have made it necessary to design a new protective device and protection circuit.
However, the conventional approach whereby trial fabrication was repeated until a target ESD immunity was satisfied is too costly, both in terms of cost and time.
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"We are excited to develop the world's first ESD protection circuit design methodology using the mixed-mode simulation", said Hironori Kitabayashi, Group Operating Officer of Semiconductor Business Group at Oki Electric.
"Applying this methodology means we can dramatically reduce development times for our high voltage LCD drivers".
"This will allow us to develop similar products with partially different process rapidly using mixed-mode simulation".
Oki has succeeded in developing this new ESD protection design methodology using mixed-mode simulation, which calibrates physical model parameters to reproduce ESD parameters extracted as operating characteristics of internal and protection devices during an ESD event.
Oki can now predict the current flow on the circuit network - something previously impossible.
Engineers who previously devoted considerable time to designing protection circuits by hand can now design circuits automatically.
Because this technique can predict the effect on protection circuits of process changes, technicians can simultaneously develop process/device design and circuit/layout design.
Furthermore, by accurately forecasting the risks of circuit performance arising in association with the process, this method can provide feedback for process/device design, reducing by one-third the overall development time required for protection circuits.
Oki's methodology has won high marks for achieving the ESD protection target (HBM 2000V and MM 200V) for high-voltage drivers for ESD protection circuits.
The paper describing this technique won best paper at the RCJ EOS/ESD/EMC Symposium and received the ESD award at the EOS/ESD Symposium in the USA - a symposium considered to be one of the highest level in the industry.
Oki was also the guest speaker at this symposium.
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