Product category: Standard Logic Devices
News Release from: National Semiconductor | Subject: DS15MB200, SCAN15MB200 and DS08MB200
Edited by the Electronicstalk Editorial Team on 16 May 2006
Multiplexer-buffers boast best signal
integrity
Dual multiplexer-buffers feature 18ps jitter performance, the best signal integrity in the industry for low-voltage differential signalling interfaces.
National Semiconductor has introduced three dual multiplexer-buffers (mux-buffers) with 18ps jitter performance, the best signal integrity in the industry for low-voltage differential signalling (LVDS) interfaces The DS15MB200, SCAN15MB200 and DS08MB200 extend the reach of LVDS signals across cables and backplanes in point-to-point applications
This article was originally published on Electronicstalk on 5 Jan 2001 at 8.00am (UK)
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The dual mux-buffer configuration manages redundant differential data streams at speeds up to 1.5Gbit/s.
Each half of the device provides a 1:2 buffer and a 2:1 multiplexer for duplicating one signal into two output streams or selecting from two alternate input data sources.
This architecture is a common building block for redundancy in serial backplanes and system interconnect applications.
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The new products' LVDS capability makes them well-suited for conditioning signals from low-cost field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), which typically do not have high-performance output drivers.
Their signal integrity features drive both data and clock signals over longer distances, enabling the use of lower-cost cables and connectors.
The small LLP package allows the devices to be placed closer to the ASIC or FPGA connector for optimum signal integrity.
In a related announcement last week, National released details of its current-mode logic (CML) signal-conditioning buffers and multiplexers with industry-leading 25ps of jitter.
With these new LVDS products, National creates a complete CML and LVDS family, allowing system designers to select the optimal interface technology and throughput, up to 4.2Gbit/s, for all their redundancy needs.
Key technical features of the DS15MB200, SCAN15MB200 and DS08MB200 The outputs of the DS15MB200 and SCAN15MB200 have configurable pre-emphasis with a separate control for each output.
Pre-emphasis conditions the signal by boosting the higher frequency components of the signal to compensate for lossy (inexpensive) backplanes or cables.
In addition, the SCAN15MB200 supports IEEE1149.1 (JTAG) and 1149.6 test features to verify connections and test the high-speed data paths.
The DS08MB200 manages datarates up to 800Mbit/s and does not include pre-emphasis or 1149.1 support.
All three dual mux-buffers include an integrated source and receiver 100ohm termination that greatly improves signal integrity by terminating the backplane or cable as close to the input/output as possible.
This reduces the external component count and board space.
The 48-pin LLP package and internal termination resistors allow the mux-buffers to offer the best combination of performance and sise for redundant LVDS signalling environments.
An on-demand online seminar, "Boosting FPGA and CPLD interface performance for offboard data transmission", is available for viewing on the National website.
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