Agere uses HSIM for ASIC timing analysis

A Nassda Corp product story

Edited by the Electronicstalk editorial team Sep 5, 2002

Agere Systems is using Nassda's HSIM hierarchical full-chip simulator and analysis tool for advanced timing analysis of clock trees and memory characterisation in its ASIC solutions.

Agere Systems is using Nassda's HSIM hierarchical full-chip simulator and analysis tool for advanced timing analysis of clock trees and memory characterisation in its ASIC solutions.

Under a multiple-licence agreement, Agere has acquired HSIM to replace existing circuit-simulation tools.

For ASIC silicon success at Agere, detailed clock-tree analysis and characterisation of advanced memories are essential.

"The power of HSIM, combined with Agere's strong clock analysis capabilities, allow Agere to provide its customers a Spice quality analysis of the clock network while staying within the standard ASIC design flow", said Don Friedberg, director of design methodologies with Agere.

"In our evaluations, HSIM proved its ability to handle our largest ASIC designs and provide the high performance, capacity and accuracy we need to address both current and emerging needs and deliver our ASIC solutions to our customers faster".

"Agere's design flow increasingly relies on the use of post-layout data in simulation and analysis", added Friedberg.

"For these kinds of simulations, HSIM has the efficiency and ease of use we require".

"For companies such as Agere that possess leading-edge ASIC communications IP capabilities, design teams are looking to solve the challenge of nanometer verification for ICs with greater circuit size and complexity", said Sang Wang, CEO of Nassda.

"We're pleased to be working with Agere to deliver HSIM with the high levels of performance, capacity and accuracy that they need to fully verify their innovative designs".