Product category: Design and Development Software
News Release from: Monterey Design Systems | Subject: IC Wizard
Edited by the Electronicstalk Editorial Team on 19 September 2002
Design planner shrinks telecomms chip
The IC Wizard hierarchical design planner has enabled the Telecommunication Network Systems Group of Fujitsu to achieve a 15% reduction in die size on a 3.3 million gate telecomms chip
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Monterey Design Systems IC Wizard hierarchical design planner has enabled the Telecommunication Network Systems Group of Fujitsu to achieve a 15% reduction in die size on a 3.3 million gate telecommunications chip. The design contains 3.3 million logic gates, 313 RAM macros, more than 10 clock domains and was fabbed on a six-metal-layer, 0.18um process technology.
The design represents a growing trend among SoC designs where more and more of the system memory is being included on the main chip, as opposed to using separate memory chips.
The presence of over 300 RAM macros made it impossible to place them manually and achieve a routable design in time to meet their schedule.
IC Wizard's block placer, not only placed the blocks automatically, but also was able to simultaneously generate multiple block placements from which Fujitsu chose the one that best met their requirements.
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This level of automation was one of the key contributors towards the 15% die size reduction.
"IC Wizard has proven to be an extremely effective design exploration tool", stated Seiji Miyoshi, Senior Manager, Communication Circuit and Device Technology Division, Telecommunication Network Systems Group, Fujitsu Limited.
"With IC Wizard, it took only two weeks to evaluate several floorplans before moving forward with on the best one.
IC Wizard allowed us to shrink the die size of the chip by 15% over what our in-house capabilities offered".
"With IC Wizard, Fujitsu was able to automate their design planning methods and achieve better results more quickly", said Rick Ader, General Manager of Japan and Asia Operations at Monterey.
"We have been able to shave the amount of upfront time they spend during this process from months to weeks, while offering significant cost savings of the chip due to the smaller size".
IC Wizard's top-down, hierarchical approach is especially well suited to handle the challenges of hierarchical SoC design.
Fujitsu found the following functionality to be particularly useful, both to improve die size and to reduce turnaround time: the ability to automatically generate multiple physical design plans very early in the design cycle prior to RTL development; the ability to automatically place blocks at any level of the design hierarchy eliminates the need to elevate the blocks to the top-level of the design purely to accommodate block placement; and the ability to handle an unlimited number of levels of hierarchy; to add or flatten levels as required to optimise for physical implementation; to move entire branches from one part of the tree to any other; and to track changes and cross probe between different representations of the same structure.
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