Product category: Design and Development Software
News Release from: Monterey Design Systems | Subject: Calypso 3.0
Edited by the Electronicstalk Editorial Team on 10 November 2003
Prototyping system predicts device performance
Calypso is the industry's first silicon virtual prototyper to combine hierarchical design planning and silicon performance estimation in a single, integrated tool
Toshiba Corp recently taped out an 8 million gate, media embedded processor (MeP) SoC using the Monterey planning and prototyping tool suite. Calypso provides the design team with the ability to accurately predict the effects of their early design decisions on the physical implementation, and to avoid problems that might be difficult or impossible to solve during implementation.
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The Calypso timing budgeting solution, which was recently used to tape out a 6 million gate design, can now make use of quick timing models (QTMs) for top-down budgeting where the resulting constraints are used to drive block-level prototyping and implementation.
Calypso can also abstract boundary models from gate-level netlists reducing the complexity of the models by as much as 70%.
This increases the capacity of the budgeting process to over 20 million gates without sacrificing accuracy.
Further reading
Upgrade accelerates physical implementation system
The Dolphin physical implementation system incorporates patented Monterey Progressive Refinement technology to simultaneously optimise a design for timing, power, area and signal integrity
The integration of design planning and prototyping makes possible capabilities such as hierarchical macro placement with full visibility through all levels of hierarchy; hierarchical timing optimisation across block boundaries; and hierarchical IR drop analysis.
Hierarchical capabilities such as these eliminate the need to optimise each block individually and resolve conflicts between the blocks at the top-level.
Additional functionality new to version 3.0 include: full rectilinear block support; flip chip support for I/O cells located within the core area of the design; flexible feedthrough capabilities during design planning; QTM generation; top level buffering based on max wire length; on-chip variation (OCV) with clock reconvergence pessimism removal (CRPR); hierarchical scan chain splitting; hierarchical clock tree synthesis; hierarchical IR drop-based STA; and hierarchical power estimation.
Calypso is shipping today on 32bit Linux, and 32 and 64bit Solaris platforms.
Calypso is priced starting at $228,000 per year.
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