Product category: Design and Development Software
News Release from: Monterey Design Systems
Edited by the Electronicstalk Editorial Team on 14 January 2002
Pair focus on
core-centric design solution
Monterey Design Systems and eASIC have entered a strategic agreement to provide the industry's first core-centric hierarchical design solution
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Record quarter for Monterey
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The combination of eASIC's eASICore configurable cores and Monterey's System-Driven Physical Design solution raises the level of physical design abstraction providing dramatic improvements in designer productivity and turnaround time. Engineers at Monterey and eASIC have been working together over the past year to develop a core-based design environment that yields significant productivity gains for large ASIC and SoC designs.
"Monterey's hierarchical methodology fits in very well with our approach of providing configurable cores for use as the basic building blocks of complex IC designs", said Zeûev Wurman, Vice President of Software at eASIC.
"We believe that the deployment of eASICores in conjunction with Monterey design tools will enable our customers to realise the goals of high-performance, rapid turnaround time, and low cost for their mission critical IC designs".
"eASICore is an ideal complement to Monterey's hierarchical methodology that uses complex cores as building blocks for multi-million gate SoC designs", said Dave Reed, Vice President of Marketing and Solutions Delivery for Monterey.
Further reading
Upgrade accelerates physical implementation system
The Dolphin physical implementation system incorporates patented Monterey Progressive Refinement technology to simultaneously optimise a design for timing, power, area and signal integrity
Prototyping system predicts device performance
Calypso is the industry's first silicon virtual prototyper to combine hierarchical design planning and silicon performance estimation in a single, integrated tool
"eASIC provides the building blocks and Monterey the tools to form an unbeatable combination that enables our customers to thrive in todayûs competitive marketplace".
One of the most challenging aspects of intellectual property (IP) reuse is integration of existing IP cores into a functional chip design.
By developing and packaging an integration environment based on Monterey's SDPD tools together with eASICores, eASIC provides a much more complete package than they would otherwise be able to offer.
The inclusion of SDPD tools dramatically reduces the time and effort required to integrate the configurable cores into complex chip designs.
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