Product category: Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial Team on 3 July 2003
Tools to support IBM foundry processes
Mentor Graphics has entered into an agreement to develop and qualify design technology files for IBM's CMOS, SiGe, RF CMOS and SOI processes
Mentor Graphics and IBM have provided Calibre design rule support for IBM foundry processes for several years. This formalised agreement expands the scope of support to deliver a complete, comprehensive set of physical verification rule files, parasitic extraction rule files and simulation models for IBM foundry processes.
This article was originally published on Electronicstalk on 3 July 2003 at 8.00am (UK)
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This support is intended to facilitate the rollout of IBM design kits providing fully integrated support for Mentor's tools throughout 2003.
Mentor Graphics will provide IBM with current and next-generation rule files for Calibre DRC, Calibre LVS (physical verification) and Calibre xRC (parasitic extraction), as well as Eldo, Eldo RF and ADVance MS models for transistor-level simulation and mixed-language simulation.
Mentor Graphics and IBM will work together to fully integrate these rule files and models into IBM's process design kits.
"IBM design kits that support tools from Mentor Graphics help drive the use of advanced manufacturing processes through accuracy, ease of use and data integrity", said Raminderpal Singh, Senior Engineering Manager for IBM Microelectronics.
"These tools are capable of handling advances in AMS SoC design and nanometre process technology, and meeting a wide range of customer requirements".
"This effort vastly expands IBM design kit support for Mentor's tools.
It significantly reduces the barriers to AMS SoC development by providing the requisite rule files and models to expedite design creation", said Anthony Nicoli, Director of Marketing for Calibre at Mentor Graphics.
"Mentor's innovative approach to verification, extraction and simulation lets designers rapidly analyse complex AMS SoC designs using accurate, mixed-level, post-layout data".
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