Product category: Design and Development Software
News Release from: Mentor Graphics UK | Subject: Seamless Version 5
Edited by the Electronicstalk Editorial Team on 17 April 2003
Coverification package analyses system performance
Version 5 of the Seamless environment extends the use of the tool beyond hardware/software coverification to system performance analysis
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The Seamless tool is the de facto standard for hardware/software coverification and new features in Version 5 enable designers to leverage data uniquely available from coverification to characterise and improve on system performance bottlenecks. Armed with the performance data provided by the Seamless tool, designers can optimise their systems by tuning designs to meet performance metrics and verifying hardware and software interfaces in a single environment.
The Seamless product is being used successfully for 32 and 64bit embedded applications in the communications, digital imaging, aerospace, and mass storage market sectors.
"The Seamless Version 5 product is a major milestone for Mentor Graphics as it extends the application of our flagship product from hardware/software coverification to system performance analysis", said Serge Leef, General Manager of the System-on-Chip Verification Division.
"With Version 5, designers can identify system bottlenecks that prevent the design from achieving or exceeding end product performance goals.
Since 1996 Seamless has been answering the question: 'Does my system work?' and now, with the release of Version 5, the Seamless tool also answers the questions: 'How well does my system work?' and 'How can I improve the system performance?'".
"The Seamless tool dramatically reduced the run-time of our regression suite, and is being used effectively to debug the hardware/software interface on our MiMagic applications processor", stated Sanjay Adkar, Vice President of Corporate Engineering for NeoMagic.
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"We consider the new performance analysis features in Version 5 a valuable addition to the Seamless environment".
The Seamless Version 5 product includes four performance characterisation windows to display different aspects of system performance.
The code-profiling window shows which software routines are taking the longest to execute.
The bus-load window shows how much bus bandwidth is being consumed by a routine and if important routines are being held up in queue.
The arbitration delay display shows how long bus masters have to wait before receiving a bus grant.
Finally, the memory-transaction display graphs memory accesses over time, including cache hits and misses.
Designers can analyse the data presented in these displays to profile a system's performance and build more efficient designs that maximise the throughput of the selected processor and bus architecture.
Beyond displaying performance data, Mentor will soon release a companion product to the Seamless Version 5 tool that automates the task of tuning system performance, once a bottleneck is exposed by the Seamless performance analysis features.
The Seamless product has extended its C hardware modelling options with support for SystemC simulation.
With native support for SystemC, designers can quickly instantiate Seamless Processor Support Packages into SystemC designs and realise the full range of Seamless benefits previously delivered only with traditional HDL cosimulation.
This complements the existing C-Bridge transaction level interface to provide the user greater flexibility in modelling hardware in C at a variety of abstraction levels.
This combination gives the designer control over the performance/accuracy tradeoffs of individual design components within their verification environment.
The Seamless Version 5 product is available now and is included as a maintenance upgrade for current Seamless licensees; there is no additional cost for this upgrade.
For new Seamless licensees, pricing starts at $40,000.
The Seamless 5 product is available now on Solaris, HP/UX and RedHat Linux platforms.
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