Product category: Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial Team on 4 November 2002
Mentor and Sharp
orchestrate Bach development
Mentor Graphics has formed a technology partnership with Sharp Corp that provides it with access to "hardware compilation" technology for rapid design and optimisation of embedded systems
Mentor Graphics has formed a technology partnership with Sharp Corp that provides it with access to "hardware compilation" technology (known publicly as the Bach system) for rapid design and optimisation of embedded systems. Development teams from Mentor Graphics and Sharp will work together to merge coverification and hardware compilation technologies to create a new set of design optimisation and analysis tools for embedded system and SoC designs.
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"This partnership advances our development of system-on-chip design and verification tools beyond the traditional capabilities of the Seamless tool, our flagship coverification product", said Serge Leef, General Manager of the System-on-Chip Verification Division at Mentor Graphics.
"Combining hardware compilation of portions of the design with advanced system integration and co-verification technologies will result in truly unique product offerings starting in 2003".
The hardware compilation technology from Sharp allows abstract descriptions of hardware in C to be simulated and synthesised into RTL.
Further reading
Functional verification expands in scope
Platform addresses low-power verification and incorporates verification management capabilities that enable closed-loop management reporting, analysis and documentation
This can be combined with the Mentor Graphics Seamless C-Bridge technology to enable efficient system level coverification of designs that include both C and HDL representations of hardware and embedded software.
This hardware compilation technology was jointly developed by Sharp Laboratories of Europe (SLE) and Sharp Corporation.
It has been used by Sharp on over 20 successful ASIC and FPGA design projects, with over half a dozen successful ASIC tape outs.
"It is exciting to see that our technology will be available outside of Sharp", said Dr Kambe, Deputy Division General Manager at Sharp's Elemental Technology Development Centre, integrated circuits Group.
"This three-way collaboration between development teams in the USA (at Mentor Graphics) and in Japan and the UK (at Sharp) will result in a design environment that allows designers to create complex system-on-chip designs much more quickly and easily".
"Combining Seamless and Bach will provide designers with a new approach to embedded system design", said Dr Paul Boca, research supervisor at Sharp's research laboratory in Europe.
"Starting from a description in untimed behavioural C, designers will be able to explore different hardware/software partitions using Seamless coverification technology from Mentor Graphics and efficiently compile hardware blocks to circuits with our hardware compilation technology".
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