Product category: Design and Development Software
News Release from: Mentor Graphics UK | Subject: Seamless for Virtex-II Pro
Edited by the Electronicstalk Editorial Team on 23 July 2002
Coverification extends to
PowerPC cores in FPGAs
Mentor Graphics is developing a customised extension to its Seamless coverification environment optimised to the needs of designers using Xilinx Virtex-II Pro Platform FPGA devices
Mentor Graphics and Xilinx are to develop a customised extension to the market-leading Seamless coverification environment, optimised to the needs of designers using Xilinx Virtex-II Pro Platform FPGA devices. Under the terms of this agreement, Mentor Graphics and Xilinx will tailor a coverification solution to the requirements of designers embedding the PowerPC 405 core into Virtex-II Pro devices.
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The collaboration result will be a coverification solution optimised for Xilinx FPGAs that will significantly ease the adoption of coverification technology into the Xilinx design flows.
The Seamless Virtex-II Pro solution builds upon the existing Seamless coverification environment and the production-proven, general-purpose PowerPC 405 Seamless processor support package (PSP).
Encapsulating knowledge of the Virtex-II Pro devices within this coverification solution significantly reduces integration time, enabling designers to be more productive in a shorter amount of time.
"Platform FPGAs with powerful embedded cores afford designers a level of integration not possible with previous generations of programmable devices", said Serge Leef, general manager of the System-on-Chip Verification Division at Mentor Graphics.
"As designers adopt this methodology they will face some of the same verification challenges associated with ASIC/SoC design.
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Seamless has proven time and again a valuable solution in simplifying and speeding this process".
Embedding processor cores into programmable devices increases the complexity of verifying such devices.
The Seamless Virtex-II Pro solution addresses these issues and simplifies the process of designing with programmable systems even further by providing designers with a virtual prototype of the platform FPGA weeks or months ahead of the time when the first physical prototypes can be programmed.
Critical to the success of verifying a complex embedded device is the ability to control and visualise the operation of the system during the debug phase.
Seamless coverification encompasses the logic simulation and software debug tools already in use in system design and verification.
Access to these tools within a virtual environment gives a level of control and observability not achievable with physical devices, not only for pre-silicon debug, but also for improved visibility when analysing problems encountered on physical prototypes.
"Xilinx is committed to providing our customers with a comprehensive debug and verification strategy to adequately address the increased system-level capability of Virtex-II Pro based designs", said Rich Sevcik, senior vice president of FPGA products at Xilinx.
"As part of our overall strategy we are pleased to work with Mentor in providing our customers with support for Seamless, a proven ASIC strength coverification tool".
The Platform FPGA will be part of a complex system that will also require verification.
Often this system will contain other processors and digital signal processors (DSPs).
Seamless offers the most comprehensive range of processor models with support for all popular embedded architectures, making Seamless the solution for both the system and device verification.
Seamless and the PowerPCT 405 PSP are available now on Solaris, HP/UX, Linux and AIX platforms.
The custom Seamless package for Xilinx Virtex-II Pro users includes the complete Seamless coverification system, the PPC405 PSP and the Virtex-II Pro IP modules and memories.
This package will be available in Q4 2002, under special one-year term licensing arrangements starting at $24,000.
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