Product category: Intellectual Property Cores
News Release from: LSI Logic Europe | Subject: 6.4Gbit/s HyperPHY core
Edited by the Electronicstalk Editorial Team on 26 January 2004
Transceiver core boasts 6.4Gbit/s throughput
A new 6.4Gbit/s Gflx (0.11-micron) HyperPHY transceiver core will help designers seeking to increase the performance and density of high-speed datacomms, telecomms and storage systems.
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LSI Logic Corporation has a new 6.4Gbit/s Gflx (0.11-micron) HyperPHY transceiver core for customers seeking to increase the performance and density of high-speed datacomms, telecomms and storage systems. Using two-level signalling (NRZ), the core contains both serialiser and deserialiser (serdes) circuitry and is available for customers as part of the company's CoreWare library for use with LSI Logic's ASIC or RapidChip platforms. "LSI Logic is committed to bringing industry-leading connectivity solutions to market.
We believe we are the first ASIC supplier to demonstrate a 6.4Gbit/s DFE transceiver solution which can be easily integrated into a custom IC", said Tom Sandoval, Vice President and General Manager of LSI Logic's Communications Products Division.
"This new addition to our HyperPHY family of products ensures we can satisfy the key decision criteria for our leading ASIC and RapidChip customers; that is performance, reliability, and flexibility".
The LSI Logic 6.4Gbit/s HyperPHY core has a wide operating range (1.2 to 6.4Gbit/s) providing the flexibility to support a number of standard datarates including Optical Interface Forum (OIF) CEI-6, XAUI, OC-48 and S-12 for applications including routers, LAN switches and SAN switches etc.
Offering best-in-class adaptive equalisation capability, the core uses DFE (decision feedback equalisation) for high-speed serial line applications, resulting in robust signal recovery and ensuring error free operation.
Additional features include the ability to use a wide range of reference clock frequencies.
LSI Logic 6.4Gbit/s transceiver technology is designed to be backward compatible to the current Gflx (0.11 micron) 3.125Gbit/s HyperPHY serdes offering providing an easy path to increase system bandwidth.
"The challenges associated with next generation terabit platforms force system designers to consider transceivers with much higher bandwidth", said Majid Bemanian, Senior Director of Marketing, Communications Products Division, LSI Logic.
"The wide operating range and two level signalling of our 6.4Gbit/s HyperPHY core provides backward compatibility, enabling solutions that interoperate with existing and next generation systems".
LSI Logic's ASIC, RapidChip and ASSP portfolio of products provide systems designers with unprecedented versatility for the development of communications, storage, and consumer products.
Customers can design scalable and expandable customised solutions by using LSI Logic's extensive library of CoreWare IP blocks, which offer proven, easy to integrate, performance-leading cores and system solutions including GigaBlaze and HyperPHY high-speed standards-compliant serdes, ARM and MIPS processors and associated systems, licensable ZSP DSP cores, processor peripherals and amba on-chip bus structures, USB cores, memory PHYs and controllers, 10/100 Ethernet PHY, 10/100/Gig MACs, PCI Express, PCI, PCI-X, PCI-X 2.0, DDR, XGXS, SPI4.2 and other protocol layer IP.
In addition, LSI Logic's world-class flxI/O flip chip ball grid array package family and standard package families provide cost-effective solutions that meet the needs of today's high-performance systems.
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