Product category: Programmable Logic Devices
News Release from: LSI Europe | Subject: RapidChip slices
Edited by the Electronicstalk Editorial Team on 4 March 2003
Slices bridge gap between
FPGAs and cell ASICs
LSI Logic has developed seven user-configurable RapidChip slices that free designers to create custom logic solutions for a broad range of applications in as little as six months
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The RapidChip family of slices provides unmatched standards-compliant serialiser/deserialiser (serdes) technology, high-performance ARM processors, and extensive logic and memory integration capabilities. The slices are aimed at the communications, storage and consumer markets. As part of the RapidChip design platform, LSI Logic's family of seven IP-rich slices address the market gap between FPGAs and cell-based ASICs by combining the benefits of both solutions; the density, performance and power found in cell-based ASICs and the fast time-to-market and lower development costs typically found in FPGAs.
"The new RapidChip slices we're announcing today underscore our commitment to provide ground-breaking technology for a broad range of applications", said Ronnie Vasishta, Vice President, ASIC Technical Marketing, LSI Logic Corporation.
"These slices open a host of opportunities for designers by giving them access to complex technology and a long list of CoreWare IP, while allowing them to hit very short market windows.
With RapidChip, engineers start much further ahead in the design process because the most complex IP is already built and proven in silicon waiting for the customer's logic".
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Features include: standards-compliant GigaBlaze serdes technology supporting several interfaces such as 1 and 10Gbit Ethernet, Fibre Channel, Serial ATA, Serial Attached SCSI and more; customer logic configured in upper layers of metal stack; user-configurable I/O pins from 304 to 638; prediffused and soft IP ARM cores including ARM7TDMI-S, ARM966E-S and ARM926EJ-S, with up to 200MHz performance, along with associated subsystems and peripherals; an easy migration path to full custom ASIC; between 500,000 and 2.5 million high-performance usable logic gates; 2Mbit of diffused RAM, offered in single- and and dual-port configurations; additional compiled memory available using configurable logic; and market-proven IP from the LSI Logic CoreWare design programme.
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