Product category: Intellectual Property Cores
News Release from: LSI Europe | Subject: DDR interface core
Edited by the Electronicstalk Editorial Team on 15 October 2002
Core interfaces SoCs with DDR SDRAM
The LSI Logic DDR core, which greatly simplifies ASIC design for interfaces to DDR SDRAM, reaches datarates up to 400Mbit/s per pin at 200MHz
This innovative, easy-to-integrate core reduces development time and design complexities. The DDR cores are ideally suited for storage, computing, printer and communications applications. "Without the LSI Logic DDR core, an ASIC designer must design an interface that meets the tight timing requirements of DDR SDRAM, a challenging, time-consuming and costly effort.
This article was originally published on Electronicstalk on 15 October 2002 at 8.00am (UK)
Related stories
LSI to shed IC assembly and test operations
Move is expected to achieve greater cost efficiencies through the adoption of a variable cost structure and to provide for scalable capacity without additional capital investment
LSI to shed consumer products business
Magnum Semiconductor is to acquire the LSI consumer products business, leaving LSI to focus its investments on its storage, networking and mobility market segments
By using this predefined and pre-verified core, our customers will realise shorter development times, lower system costs and greater performance and reliability", stated Dave Jones, vice president and general manager of LSI Logic's Storage and Computing ASIC Division.
"Demand is high for reliable interfaces between ASICs and high-speed DDR SDRAM.
LSI Logic is delivering this valuable technology today, and we'll continue to offer next generation cores as customer needs evolve".
"LSI Logic provided HP with a complete, preverified DDR core that handled the critical timing in our ASIC DRAM interface", said Rick Klaus, Senior Design Engineer, HP Imaging and Printing Group.
"This enabled us to more rapidly complete our memory controller design".
Further reading
Modem chipsets embed flexible communications
An all-new line of embedded modem products includes a pin-compatible family of data and fax modem chipsets and a single package monolithic data access arrangement
Comms processors use carrier-class technology
New generation of advanced communication processors will enable network equipment designers to provide high-bandwidth and real-time services
LSI releases sluggish Q1 results
Chip maker's first quarter results show reduced revenue compared with last year's figures
The LSI Logic DDR interface core is available in the company's G12 0.18-micron and Gflx 0.11-micron process technologies, leveraging LSI Logic's extensive expertise in high performance I/O interfaces.
The core provides a robust physical layer interface to high performance DDR SDRAM memory and uses a simple ASIC side interface.
The ASIC designer has the flexibility to use a performance-optimised DDR memory controller from LSI Logic, an internal memory controller or a third party memory controller.
"The G12 DDR core has been fully characterised with test chips and in several of our customer's products, meeting the 200MHz specification with plenty of margin", said Khanh Le, Vice President of High Speed Interface Engineering at LSI Logic.
The DDR SDRAM core is offered as a hardmac with preverified layout and timing.
The 8bit-wide core can be used in parallel to scale up to 32bit, 64bit and higher bus widths, giving designers the greatest flexibility.
Based on today's industry standards, the core allows designers to read and write DDR SDRAM memories in point-to-point and dual in-line memory module (DIMM) configurations.
The DDR cores are part of the LSI Logic CoreWare design program, an extensive library of pre-designed and pre-verified cores that can be easily integrated with customer-designed logic.
The CoreWare program reduces development time and overall system cost while increasing system performance and reliability.
Customer designs with the LSI Logic DDR cores are already underway.
The DDR interface core is also available in LSI's recently announced RapidChip semiconductor platform for fast SoC designs.
• LSI Europe: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• NEW
• Electronicstalk Home Page
Related Business News
Cast Selects Avery Design Systems For...
...Pci Express Verification Ip. Semiconductor intellectual property provider CAST, Inc. today announced that it has begun using the PCI-Xactor test environment from Avery Design Systems to verify its current and future PCI Express IP cores.
Vsia Announces Release Of Qip Metric...
...Now Publicly Available With Hard Ip Extension. The VSI Alliance , the leading IP standards body for the electronics industry, today announced the Quality IP Metric version 3.0, which includes the hard IP extension, is now publicly available.
Gda Technologies Selected By Renesas Technology...
...For Pci Express To Amba Axi Bridge. Gda Technologies, Inc., a fast growing supplier of Intellectual Property and Electronic Design Services , today announced that Renesas Technology Corp., a leading semiconductor company, has selected GDA for development of a PCIE 2 AMBA AXI Bridge to be
Altera delivers first FPGA-Based IP support for Ethernet protocols
Bangalore, India: Altera Corp. has announced FPGA-based support for Ethernet communications protocols used in industrial automation applications, including ProfiNet, Ethernet/IP, Modbus-IDA, EtherCAT, SERCOS III Interface, and Ethernet Powerlink.
Ieee Picks Up Vsia's Standards Work
The IEEE has formed two study groups to explore the creation of IEEE standards based on work done at the VSI Alliance.
Search the Pro-Talk network of sites
