Product category: Communications ICs (Wired)
News Release from: LSI Europe | Subject: Ultra HyperPHY
Edited by the Electronicstalk Editorial Team on 8 May 2002
Ultra-fast transceivers run
up to 3.2Gbit/s
LSI Logic has released its Ultra HyperPHY transceiver technology for next generation broadband transmission and networking ASICs requiring multiple high-speed data transfer channels
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operating from 2.4 to 3.2Gbit/s. Offering a combination of low power dissipation and high performance, the Ultra HyperPHY 0.11-micron CMOS modular architecture allows for customer specific ASIC designs to best meet the target system application. LSI Logic's Ultra HyperPHY technology provides an ideal solution to the backplane bandwidth bottleneck in high throughput Sonet/SDH crossconnects and dense wavelength division multiplexing systems as well as in high- bandwidth ATM and LAN switches.
"Our Ultra HyperPHY technology is designed to support the emerging needs of very high levels of integration and ultra high speed interfaces in ASICs for communication applications", said Dr Hemant Thapar, senior vice president, Communications Technology, LSI Logic.
"In a single chip, designers can include as many as 128 full-duplex independent channels, thereby supporting interface bandwidths in excess of 800Gbit/s.
By combining the high performance, low power, small area and cost advantages of Ultra HyperPHY technology with the ease of use of LSI Logic's CoreWare methodology and sophisticated modelling support for LSI Logic's HyperPHY cores, customers can easily and quickly get to market with system-level ASIC solutions".
As more and more line cards are fitted into a switch box, the distance a signal needs to travel across a backplane increases.
With LSI Logic's Ultra HyperPHY transceivers, it is feasible to drive 3.2Gbit/s signals across trace lengths up to 1m on standard FR-4 material.
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The Ultra HyperPHY CML driver is programmable for both output swing and pre-emphasis, allowing the designer unprecedented flexibility in configuring the system for optimal performance.
LSI Logic system engineers can provide extensive backplane modelling support for systems using HyperPHY transceivers to predict end-to-end performance in a simulation-based "rapid prototyping" environment.
This service to customers can minimise or even eliminate board problems due to high-speed signaling, decreasing the time-to-market of the end product.
As a principal member of the Optical Internetworking Forum (OIF), LSI Logic has designed the Ultra HyperPHY transceiver to be fully compliant with the OIF SxI-5 electrical interface specification.
Coupled with the modular HyperPHY architecture, LSI Logic supports the emerging SPI-5 and SFI-5 interfaces and their narrow band derivatives.
The Ultra HyperPHY CML drivers and receivers are also compatible with the XAUI electrical standard for many applications.
Ultra HyperPHY transceivers can run in half- and quarter-rate modes, allowing bridging to previous generation systems operating at lower rates.
The HyperPHY clock and data recovery design supports both unencoded and 8B/10B encoded data streams.
The Ultra HyperPHY cores provide physically separate transmit and receive (with clock recovery) functions.
An application can have all transmit channels on one side of a die and all receive channels on another side of the die and still provide at-speed built-in-self-test, an important production test feature.
The core modularity allows any combination of transmit and receive channels up to 128 on an ASIC.
These HyperPHY "subsystems" are constructed by LSI Logic CoreWare engineers per customer direction.
"Backplanes and transceivers are used in almost all networking systems, including switches, routers, cross connects, add/drop multiplexers, DSLAMs and optical networking equipment, among others", said Sherry Garber, Senior Vice President, Semico Research Corporation.
"The backplane, where all data is aggregated and switched, has become the most critical intra-system bandwidth bottleneck.
LSI Logic is addressing these specific challenges and is delivering a technology with a substantial increase in performance and integration".
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