Product category: Intellectual Property Cores
News Release from: LSI Europe | Subject: SPI-4 Phase 2 IP core
Edited by the Electronicstalk Editorial Team on 27 March 2002
Interface core ready
for 10Gbit Ethernet
LSI Logic has released a System Packet Interface Level 4 (SPI-4) Phase 2 intellectual-property (IP) core aimed at communications and storage markets
System level designs based on the company's SPI-4 Phase 2 core will allow designers to design their ASICs with verified interoperability, significantly simplifying interface design and reducing time-to-market of high speed networking applications. The SPI-4 Phase 2 core operates up to 800MHz and allows the implementation of 12.8Gbit/s throughput on the system bus.
This article was originally published on Electronicstalk on 27 March 2002 at 8.00am (UK)
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The core has been optimised for use in emerging applications requiring 10Gbit Ethernet, OC-192 Sonet and packet-over-Sonet (PoS).
Recently named by IDC as the top vendor in both local and wide area networks, LSI Logic is continuing this success with several SPI-4 Phase 2 designs in development with key industry leaders.
"LSI Logic understands that its customers need complete solutions that are scalable, versatile, and reliable", said Tom Sandoval, vice president of LSI Logic Communications Marketing.
"Having the SPI-4 Phase 2 core in our rich CoreWare library provides networking system architects the intellectual property they need to satisfy the explosive growth of gigabit Ethernet and optical networking equipment requirements and has proven critical for helping them manage their increasing time to market pressures".
As a principal member of the Optical Internetworking Forum (OIF) (www.oiforum.com), LSI Logic is actively participating in the development and deployment of interoperable products and services for data switching and routing using optical networking technologies.
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The SPI-4 Phase 2 core can be used to upgrade to paths that incorporate new and evolving technologies into existing networks.
With a complete roadmap of products based on the SPI standards, LSI Logic simplifies the design of high-speed interfaces for its ASICs and ASSPs.
"The rapid growth of data traffic over the Internet has created a new wave of designs for next generation high speed switches", said Sandoval.
"SPI-4 Phase 2 is proving to be the high speed interface standard with the most momentum in our current customer designs".
With LSI Logic's SPI-4 Phase 2 core and the company's proven CoreWare methodology, designers can meet stringent time-to-market requirements and develop SPI-4 Phase 2 based ASICs rapidly.
The CoreWare design programme provides a complete set of deliverables to ensure successful integration of IP building blocks into complex ASICs or SoC designs.
It has made core reuse a reality through a design methodology that is optimised for an ASIC design environment.
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